STM32 - 高级定时器的设定 - 基础-05 - 输出波形控制 -Complementary outputs and dead-time insertion 相位调整@互补输出和死区控制
The advanced-control timers (TIM1 and TIM8) can output two complementary（互补） signals and manage the switching-off and the switching-on instants of the outputs. This time is generally known as dead-time and it has to be adjust it depending on the devices connected to the outputs and their characteristics (intrinsic delays of level-shifters, delays due to power switches...)
User can select the polarity of the outputs (main output OCx or complementary OCxN) independently for each output.
This is done by writing to the CCxP and CCxNP bits in the TIMx_CCER register.
TIMx_CCER 使能控制寄存器，控制CCxP 、CCxNP ，
Bit 1 CC1P: Capture/Compare 1 output polarity
CC1 channel configured as output:
0: OC1 active high
1: OC1 active low
Bit 3 CC1NP: Capture/Compare 1 complementary output polarity
0: OC1N active high.
1: OC1N active low.
The complementary signals OCx and OCxN are activated by a combination of several control bits:
- the CCxE and CCxNE bits in the TIMx_CCER register
OC/OCN输出使能控制
Bit 0 CC1E: Capture/Compare 1 output enable
CC1 channel configured as output:
0: Off - OC1 is not active. OC1 level is then function of MOE, OSSI, OSSR, OIS1, OIS1N and CC1NE bits.
1: On - OC1 signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS1, OIS1N and CC1NE bits.
Bit 2 CC1NE: Capture/Compare 1 complementary output enable
0: Off - OC1N is not active. OC1N level is then function of MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits.
1: On - OC1N signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits.
- and the MOE, OISx, OISxN, OSSI and OSSR bits in the TIMx_BDTR
TIM1 and TIM8 break and dead-time register (TIMx_BDTR)
Bit 15 MOE: Main output enable
This bit is cleared asynchronously by hardware as soon as the break input is active. It is set by software or automatically depending on the AOE bit. It is acting only on the channels which are configured in output.
0: OC and OCN outputs are disabled or forced to idle state.
1: OC and OCN outputs are enabled if their respective enable bits are set (CCxE, CCxNE in TIMx_CCER register).
See OC/OCN enable description for more details (Section 14.4.9: TIM1 and TIM8 capture/compare enable register (TIMx_CCER)).
Bit 11 OSSR: Off-state selection for Run mode
This bit is used when MOE=1 on channels having a complementary output which are configured as outputs. OSSR is not implemented if no complementary output is implemented in the timer.
See OC/OCN enable description for more details (Section 14.4.9: TIM1 and TIM8 capture/compare enable register (TIMx_CCER)).
0: When inactive, OC/OCN outputs are disabled (OC/OCN enable output signal=0).
1: When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1
or CCxNE=1. Then, OC/OCN enable output signal=1
Bit 10 OSSI: Off-state selection for Idle mode
This bit is used when MOE=0 on channels configured as outputs.
See OC/OCN enable description for more details (Section 14.4.9: TIM1 and TIM8 capture/compare enable register (TIMx_CCER)).
0: When inactive, OC/OCN outputs are disabled (OC/OCN enable output signal=0).
1: When inactive, OC/OCN outputs are forced first with their idle level as soon as CCxE=1 or CCxNE=1. OC/OCN enable output signal=1)
Bits 7:0 DTG[7:0]: Dead-time generator setup
This bit-field defines the duration of the dead-time inserted between the complementary outputs. DT correspond to this duration.
DTG[7:5]=0xx => DT=DTG[7:0]x tdtg with tdtg=tDTS.
DTG[7:5]=10x => DT=(64+DTG[5:0])xtdtg with Tdtg=2xtDTS.
DTG[7:5]=110 => DT=(32+DTG[4:0])xtdtg with Tdtg=8xtDTS.
DTG[7:5]=111 => DT=(32+DTG[4:0])xtdtg with Tdtg=16xtDTS.
Example if TDTS=125ns (8MHz), dead-time possible values are:
0 to 15875 ns by 125 ns steps,
16 us to 31750 ns by 250 ns steps,
32 us to 63us by 1 us steps,
64 us to 126 us by 2 us steps
- and TIMx_CR2 registers.
for more details. In particular, the dead-time is activated when switching to the IDLE state (MOE falling down to 0). Dead-time insertion is enabled by setting both CCxE and CCxNE bits, and the MOE bit if the break circuit is present. DTG[7:0] bits of the TIMx_BDTR register are used to control the dead-time generation for all channels.
From a reference waveform OCxREF, it generates 2 outputs OCx and OCxN. If OCx and OCxN are active high:
• The OCx output signal is the same as the reference signal except for the rising edge, which is delayed relative to the reference rising edge.（见下面分析）
• The OCxN output signal is the opposite of the reference signal except for the rising edge, which is delayed relative to the reference falling edge.（见下面分析）
If the delay is greater than the width of the active output (OCx or OCxN) then the corresponding pulse is not generated.
The following figures show the relationships between the output signals of the dead-time generator and the reference signal OCxREF. (we suppose CCxP=0, CCxNP=0, MOE=1, CCxE=1 and CCxNE=1 in these examples)
CC1P=0 ----> 0: OC1 active high
CC1NP =0 ----> : 0: OC1N active high.
MOE=1 ----> 1: OC and OCN outputs are enabled
CCxE=1 ----> 1: On - OC1 signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS1, OIS1N and CC1NE bits.
CCxNE=1 ----> 1: On - OC1N signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits.
笔者案：我们现在依据上面的这个例子来分析一下：
• The OCx output signal is the same as the reference signal except for the rising edge, which is delayed relative to the reference rising edge
首先看OCX的输出，他应该是完全和OCXREF的输出一致，除了，上升沿会增加死区延时：
蓝色为相同部分，后面上升沿往后移动了一格设定的delay时间。
• The OCxN output signal is the opposite of the reference signal except for the rising edge, which is delayed relative to the reference falling edge.（见下面分析）
The dead-time delay is the same for each of the channels and is programmable with the DTG bits in the TIMx_BDTR register.
delay的时间通过DTG来控制。
Re-directing OCxREF to OCx or OCxN
In output mode (forced, output compare or PWM), OCxREF can be re-directed to the OCx output or to OCxN output by configuring the CCxE and CCxNE bits in the TIMx_CCER register.
将输出的OCXREF的波形可以转接到OCX 等其他端口，
This allows the user to send a specific waveform (such as PWM or static active level) on one output while the complementary remains at its inactive level. Other possibilities are to have both outputs at inactive level or both outputs active and complementary with dead-time.
Note: When only OCxN is enabled (CCxE=0, CCxNE=1), it is not complemented and becomes active as soon as OCxREF is high. For example, if CCxNP=0 then OCxN=OCxRef. On the other hand, when both OCx and OCxN are enabled CCxE=CCxNE=1) OCx becomes active when OCxREF is high whereas OCxN is complemented and becomes active when
OCxREF is low.