Using Clock Signal To Make Multiple Divider --- Verilog Learning Notes

**

Using Clock Signal To Make Multiple Divider — Verilog Learning Notes

**

Making Multiple Divider is the elementary task for a FPGA engineer and this passage briefly introduce how to use clock signal to design divider. This passage is only used for me to study and all amateurs to communicate.

It is easy to make an even number divider by simply using the posedge or negedge invertion of the clock signal. For a frequency divide-by-2, the Verilog code is like below

For the frequency diversion larger than 2, we can using a counter for the even number we need to make it. The principle is just as same as above. Let the value of divider change every time your counter meet the flip point. For instance, if you need a divide by four, your divider’s value change every time the counter is add up to 2 and reset it to 0.

The hard part for the mutiple divider is the odd number divider such as divide by three counter. Most time your teacher or boss want you to make a odd number dividerwith duty circle 0.5. And it is not possible to make this signal with only one cloick signal. Therefore, using two clock signal for a 0.5 duty circle is very useful for this design. Let’s watch this figure to have a further understanding on how to use two clock signal.

While we use two colck signal one flip at the posedge of the clock signal and the other flip at the negedge we got the figure above. And this is the key point to make an odd number divider. we can see that by using those two signal, we got two even divider with a half clock cycle phase differences. Which means if we use or operation we can get an odd divider. In this case the author write a didvide by 7 counter and the code is shown below.

The interval can be defined by yourself but remember it cannot beyond the limit of your counter and your interval should include (N-1)/2(N is the odd number) cycles.