The TIMx timers are linked together internally for timer synchronization or chaining. When one Timer is configured in Master Mode, it can reset, start, stop or clock the counter of another Timer configured in Slave Mode.

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Figure 140 presents an overview of the trigger selection and the master mode selection blocks.

Note: The clock of the slave timer must be enabled prior to receiving events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer

For example, the user can configure Timer 1 to act as a prescaler for Timer 2 (see Figure 140). To do this:

• Configure Timer 1 in master mode so that it outputs a periodic （周期）trigger signal on each update event UEV. If you write MMS=010 （Event Update as trigger）in the TIM1_CR2 register, a rising edge is output on TRGO1 each time an update event is generated.

设置Master T1的Event 输出为触发信号

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定时器控制寄存器2

Bits 6:4 MMS[2:0]: Master mode selection

These bits allow to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows:

000: Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset.

001: Enable - the Counter enable signal, CNT_EN, is used as trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic OR between CEN control bit

and the trigger input when configured in gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR register).

010: Update - The update event is selected as trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer.

011: Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred.

(TRGO)

100: Compare - OC1REF signal is used as trigger output (TRGO)

101: Compare - OC2REF signal is used as trigger output (TRGO)

110: Compare - OC3REF signal is used as trigger output (TRGO)

111: Compare - OC4REF signal is used as trigger output (TRGO)

Note: The clock of the slave timer and ADC must be enabled prior to receiving events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer.

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• To connect the TRGO1 output of Timer 1 to Timer 2, Timer 2 must be configured in slave mode using ITR0 as internal trigger. You select this through the TS bits in the TIM2_SMCR register (writing TS=000). 级联T1 &T2

定时器主从模式控制寄存器

Bits 6:4 TS: Trigger selection

This bit-field selects the trigger input to be used to synchronize the counter.

000: Internal Trigger 0 (ITR0).

001: Internal Trigger 1 (ITR1).

010: Internal Trigger 2 (ITR2).

011: Internal Trigger 3 (ITR3).

100: TI1 Edge Detector (TI1F_ED)

101: Filtered Timer Input 1 (TI1FP1)

110: Filtered Timer Input 2 (TI2FP2)

111: External Trigger input (ETRF)

See Table 86: TIMx Internal trigger connection for more details on ITRx meaning for each Timer.

• Then you put the slave mode controller in external clock mode 1 (write SMS（Slave mode selection）=111 in the TIM2_SMCR register). This causes Timer 2 to be clocked by the rising edge of the periodic Timer 1 trigger signal (which correspond to the timer 1 counter overflow).

Timer 主从控制寄存器，将T2配置为从模式，并且，为外部时钟模式，在TRGI的上升沿作为clock的计数，

Bits 2:0 SMS: Slave mode selection

When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description.

000: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock.

001: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.

010: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.

011: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.

100: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.

101: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.

110: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.

111: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.

• Finally both timers must be enabled by setting their respective CEN bits (TIMx_CR1 register). 然后使能两个定时器

Note: If OCx is selected on Timer 1 as trigger output (MMS=1xx), its rising edge is used to clock the counter of timer 2.

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Using one timer to enable another timer

In this example, we control the enable of Timer 2 with the output compare 1 of Timer 1.

Refer to Figure 140 for connections. Timer 2 counts on the divided internal clock only when OC1REF of Timer 1 is high. Both counter clock frequencies are divided by 3 by the prescaler compared to CK_INT (fCK_CNT = fCK_INT/3).这个例子将T2的计数使能放置在T1的输出波形的高起作用。同时，有3分频的设置。

• Configure Timer 1 master mode to send its Output Compare 1 Reference (OC1REF) signal as trigger output (MMS=100 in the TIM1_CR2 register).

定时器寄存器控制2，设定MMS,主定时器模式选择器，T1的输出先配置好，作为触发的输出

100: Compare - OC1REF signal is used as trigger output (TRGO)

• Configure the Timer 1 OC1REF waveform (TIM1_CCMR1 register).

定时器模式控制器，配置T1 的输出波形模式

• Configure Timer 2 to get the input trigger from Timer 1 (TS=000 in the TIM2_SMCR register).

主从控制模式寄存器，设置T2为的触发模式为内部定时器触发，

000: Internal Trigger 0 (ITR0). ITR0 支持Timer1

• Configure Timer 2 in gated mode (SMS=101 in TIM2_SMCR register).

主从控制模式寄存器，配置T2为门模式，T2的 SMS 从模式选择

1: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.

• Enable Timer 2 by writing ‘1 in the CEN bit (TIM2_CR1 register).

• Start Timer 1 by writing ‘1 in the CEN bit (TIM1_CR1 register).

Note: The counter 2 clock is not synchronized with counter 1, this mode only affects the Timer 2 counter enable signal.

Figure 14

In the example in Figure 141, the Timer 2 counter and prescaler are not initialized before being started. So they start counting from their current value. It is possible to start from a given value by resetting both timers before starting Timer 1. You can then write any value you want in the timer counters. The timers can easily be reset by software using the UG bit in the TIMx_EGR registers.

该例子的高级用法，就是因为T2 CNT保持不变，那么软件可以就需求进行定制。