SDR SDRAM & DDR SDRAM CHAPTER 1：SDR SDRAM 和 DDR SDRAM 的不同

CHAPTER 1：SDR SDRAM 和 DDR SDRAM 的不同

DDR SDRAM (double data rate synchronous DRAM) ：双速率同步动态随机存储器

SDR SDRAM (single data rate synchronous DRAM)：单速率同步动态随机存储器

1.1 Data transfer frequency, data rate
DDR SDRAM：data transfer rate that is twice the clock frequency 数据速率是时钟频率的两倍，上升边和下降边均采样（为了在采样时更加精准的控制存储器，采用差分时钟）
SDR SDRAM：数据速率 和时钟频率相等，上升边采样（单端时钟，采样时预留的裕量较大，采用单端时钟）

1.2 Interface

DDR SDRAM：SSTL_2 (Stub Series Terminated Logic for 2.5V)。特点：低电压、低摆幅、高速接口、使用串联的Stub电阻来抵消反射信号。SSTL-2 is a low-voltage (2.5V), small-amplitude and high-speed interface that reduces the effect of reflection by connecting series resistance between the signal branch point from the bus (stub) and the memory.
(1) Stub resistance：Stub电阻串接在Vout电源上，主要实现传输线和设备输出之间的阻抗匹配。A stub resistance of approximately 25Ω (22Ω is generally used for DIMMs (Dual In-Line Memory Modules)) is connected in series to the output pin (VOUT), providing impedance matching between the transmission line and device output.
(2) Termination voltage：端接电阻用来削弱传输线上面的信号反射，减小电压突变。This termination suppresses signal reflection in the transmission line and also reduces voltage spikes, enabling highspeed data transmission.
(3) Reference voltage： SSTL_2 interface接口的高低电平相互对称，参考电阻为电平提供一个参考。The SSTL_2 interface is symmetrical with respect to high-level and low-level output. VREF is used as a reference voltage to detect high and low levels.

 

1.3 Power supply

2.5V的低电压减小了电源损耗。Compared to the 3.3V power supply of SDR SDRAM, the power supply of DDR SDRAM is 2.5V. This reduction in power supply voltage reduces the power consumption of the DDR SDRAM circuits.
1.4DLL(Delay Locked Loop) ——参考阅读《高速信号测试原理与指南》
动态调整内外部时钟之间的延迟。The DLL circuit is designed to realize a fast access time and high operation frequencies by controlling and adjusting the time lag between the external clock and internal clock。By employing DLL, timing skew between the clock (CK, /CK) and DQ/DQS is minimized.
容量计算：nM words × m bits × z banks