FPGA 时序约束 三 :输入延迟和输出延迟
时序分析是建立在时序约束的基础之上。FPGA设计有4类时序路径的起点和终点:
一个完整的时序路径由源时钟路径、数据路径和目的时钟路径2部分构成。约束的目的则是为了验证下面公式是否成立:
Tco为发端寄存器时钟到输出时间;Tlogic为组合逻辑延迟;Trouting为两级寄存器之间的布线延迟;Tsu为接收端寄存器建立时间;Tskew为两级寄存器的时钟歪斜,其值等于时钟统一边沿到达两个寄存器时钟端口的时间差;Tclk为系统所能达到的最小时钟周期。在FPGA中,对于同步设计Tskew可忽略(认为值等于0)。由于Tco和Tsu取决于芯片工艺,因此,一旦芯片型号选定就只能通过Tlogic和Trouting来改善Tclk。其中,Tlogic和代码风格有很大关系,Trouting和布局布线策略有很大关系。
前面讲了FPGA内部常用的时序约束,为了对设计外部的时序情况进行精确建模,设计者必须设定输入和输出端口的时序信息。Vivado只能识别出FPGA器件范围内的时序,因此必须使用set_input_delay和set_output_delay命令来设置FPGA范围外的延迟值。两者在含义、约束命令等方面有很多地方是相似的,只不过一个是输入,一个是输出。
输入输出约束还是使用vivado 自带language来约束
System Synchronous Input
分析输入端口到FPGA内部时序单元的路径时,当source clock和destination clock来自同一个系统时钟时,称为系统同步输入(system synchronous input)。
源同步需要时钟和数据来自同一个源,系统同步中只要求source clock和destination clock来自同一个时钟网络即可。
如图1所示为系统同步输入,source clock是CLKA,destination clock是CLKB,其中CLKB通过输入端口引入FPGA内部(约束成主时钟),而CLKA引到了FPGA外部的板上芯片,并没有引入到FPGA内部,CLKB是采集输入端口的时钟。
Source Synchronous Input
分析输入端口到FPGA内部时序单元的路径时,当destination clock来自外部芯片,即与数据输入同源,称为源同步输入(source synchronous input)。
结构如图2所示,从板上芯片输入到FPGA除了有数据,还有一个随路时钟,是由板上芯片产生的。。
下述描述的公式中:
Tco ---- 外部芯片的 Tco,Tco的参数通常需要查外部芯片的数据手册。
Trce--- 板间线路延迟。根据时钟频率和线长来确定。但是数这里通常都设置为0
系统同步约束
1)系统同步SDR rising
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# Rising Edge System Synchronous Inputs 系统同步输入上升沿触发
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#
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# A Single Data Rate (SDR) System Synchronous interface is
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# an interface where the external device and the FPGA use
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# the same clock, and a new data is captured one clock cycle
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# after being launched
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# 系统同步接口SDR是外部器件和FPGA采用相同的时钟,新的数据在触发后一个时钟周期被捕获
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# iput __________ __________
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# clock __| |__________| |__
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# |
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# |------> (tco_min+trce_dly_min)
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# |------------> (tco_max+trce_dly_max)
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# __________ ________________
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# data __________XXXXXX_____ Data _____XXXXXXX
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#
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set input_clock <clock_name>; # Name of input clock
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set tco_max 0.000; # Maximum clock to out delay (external device)
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set tco_min 0.000; # Minimum clock to out delay (external device)
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set trce_dly_max 0.000; # Maximum board trace delay 板间线路延迟
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set trce_dly_min 0.000; # Minimum board trace delay
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set input_ports <input_ports>; # List of input ports
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# Input Delay Constraint
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set_input_delay -clock $input_clock -max [expr $tco_max + $trce_dly_max] [get_ports $input_ports];
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set_input_delay -clock $input_clock -min [expr $tco_min + $trce_dly_min] [get_ports $input_ports];
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# Report Timing Template
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# report_timing -from [get_ports $input_ports] -max_paths 20 -nworst 1 -delay_type min_max -name sys_sync_rise_in -file sys_sync_rise_in.txt;
知道了tco trce_dly 的值,也可以直接使用下面对应参数直接代入公式即可。
set_input_delay -clock $input_clock -max [expr $tco_max + $trce_dly_max] [get_ports $input_ports];
2)系统同步SDR falling
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set_input_delay -clock $input_clock -max [expr $tco_max + $trce_dly_max] [get_ports $input_ports] -clock_fall;
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set_input_delay -clock $input_clock -min [expr $tco_min + $trce_dly_min] [get_ports $input_ports] -clock_fall;
3) 系统同步DDR
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# DDR System Synchronous Inputs
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#
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# A Double Data Rate (DDR) System Synchronous interface is
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# an interface where the external device and the FPGA use
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# the same clock, and a new data is captured half a clock
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# cycle after being launched
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#
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# input _______________________________ ________
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# clock _| |________________________________|
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# | |
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# |-> (trco_min+trce_dly_min) |-> (tfco_min+trce_dly_min)
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# |-----> (trco_max+trce_dly_max) |-----> (tfco_max+trce_dly_max)
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# ____ ____________________________ ____________________________ ___
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# data ____XXXX__________Rise_Data_________XXXX__________Fall_Data_________XXXX___
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#
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set input_clock <clock_name>; # Name of input clock
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set trco_max 0.000; # Maximum clock to output delay from rising edge (external device)
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set trco_min 0.000; # Minimum clock to output delay from rising edge (external device)
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set tfco_max 0.000; # Maximum clock to output delay from falling edge (external device)
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set tfco_min 0.000; # Minimum clock to output delay from falling edge (external device)
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set trce_dly_max 0.000; # Maximum board trace delay
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set trce_dly_min 0.000; # Minimum board trace delay
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set input_ports <input_ports>; # List of input ports
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# Input Delay Constraint
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set_input_delay -clock $input_clock -max [expr $trco_max + $trce_dly_max] [get_ports $input_ports];
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set_input_delay -clock $input_clock -min [expr $trco_min + $trce_dly_min] [get_ports $input_ports];
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set_input_delay -clock $input_clock -max [expr $tfco_max + $trce_dly_max] [get_ports $input_ports] -clock_fall -add_delay;
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set_input_delay -clock $input_clock -min [expr $tfco_min + $trce_dly_min] [get_ports $input_ports] -clock_fall -add_delay;
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# Report Timing Template
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# report_timing -rise_from [get_ports $input_ports] -max_paths 20 -nworst 2 -delay_type min_max -name sys_sync_ddr_in_rise -file sys_sync_ddr_in_rise.txt;
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# report_timing -fall_from [get_ports $input_ports] -max_paths 20 -nworst 2 -delay_type min_max -name sys_sync_ddr_in_fall -file sys_sync_ddr_in_fall.txt;
源时钟同步
源同步是为了消除系统同步中频率受限的不足而发展而来的,在发送端将数据和时钟同步传输,在接收端用时钟沿锁存数据;理论上源同步不受传输延迟的影响。源同步除了SDR、DDR的分别外,由于clk和data同时传输,源同步还分clk和data中心对齐和边缘对齐。
1)源同步SDR 中心对齐
从下面的时序图中可以看到,中心对齐就是时钟在数据跳变的中间。
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# Center-Aligned Rising Edge Source Synchronous Inputs
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#
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# For a center-aligned Source Synchronous interface, the clock
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# transition is aligned with the center of the data valid window.
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# The same clock edge is used for launching and capturing the
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# data. The constraints below rely on the default timing
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# analysis (setup = 1 cycle, hold = 0 cycle).
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#
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# input ____ __________
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# clock |_________| |_____
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# |
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# dv_bre | dv_are
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# <------>|<------>
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# __ ________|________ __
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# data __XXXX____Rise_Data____XXXX__
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#
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set input_clock <clock_name>; # Name of input clock
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set input_clock_period <period_value>; # Period of input clock
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set dv_bre 0.000; # Data valid before the rising clock edge
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set dv_are 0.000; # Data valid after the rising clock edge
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set input_ports <input_ports>; # List of input ports
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# Input Delay Constraint
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set_input_delay -clock $input_clock -max [expr $input_clock_period - $dv_bre] [get_ports $input_ports];
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set_input_delay -clock $input_clock -min $dv_are [get_ports $input_ports];
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# Report Timing Template
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# report_timing -from [get_ports $input_ports] -max_paths 20 -nworst 1 -delay_type min_max -name src_sync_cntr_rise_in -file src_sync_cntr_rise_in.txt;
同类的还有下降沿同步,这里省略,具体看language里面的介绍。
2)源同步SDR 边缘对齐
边沿对齐又分两种情况:clock with MMCM 和 clock directly to FF。字面意思上理解一个是经过MMCM锁相环之类的时钟,一个是FF触发器的时钟。具体看有关延迟的指令,两个的计算公式都不一样,clock directly to FF 还需要时钟周期,但是MMCM只有时钟偏斜即可。
边缘对齐是指时钟和数据到达后级时序单元时,时钟沿与数据变化沿重合,如下图所示:
这种情况下显然不满足后级时序单元的Setup要求,因此时钟需要经过一定的移相才能去采集数据,通常采用MMCM模块实现移相,
时钟约束如下:
create_clock -name CLKB -period clk_period [get_ports {CLKB}]
create_generated_clock -name CLKB_90 -source [get_clocks CLKB] –phase 90 [get_pins{MMCM|co[0]}]
set_input_delay -clock[get_clocks CLKB_90] -max max_input_delay [get_ports indata]
set_input_delay -clock[get_clocks CLKB_90] -min min_input_delay [get_ports indata] -add_delay
clock with MMCM
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# Edge-Aligned Rising Edge Source Synchronous Inputs
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# (Using an MMCM/PLL)
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#
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# For an edge-aligned Source Synchronous interface, the clock
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# transition occurs at the same time as the data transitions.
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# In this template, the clock is aligned with the end of the
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# data. The constraints below rely on the default timing
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# analysis (setup = 1 cycle, hold = 0 cycle).
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#
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# input __________ ________________
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# clock |________________| |__________
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# |
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# skew_bre|skew_are
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# <------>|<------>
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# _________________ | _________________
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# data XX____Rise_Data____XXXXXXXXXXXXXXXXX_________________XX
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#
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set input_clock <clock_name>; # Name of input clock
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set skew_bre 0.000; # Data invalid before the rising clock edge
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set skew_are 0.000; # Data invalid after the rising clock edge
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set input_ports <input_ports>; # List of input ports
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# Input Delay Constraint
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set_input_delay -clock $input_clock -max $skew_are [get_ports $input_ports];
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set_input_delay -clock $input_clock -min -$skew_bre [get_ports $input_ports];
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# Report Timing Template
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# report_timing -from [get_ports $input_ports] -max_paths 20 -nworst 1 -delay_type min_max -name src_sync_edge_rise_in -file src_sync_edge_rise_in.txt;
clock directly to FF
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# Edge-Aligned Rising Edge Source Synchronous Inputs
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# (Using a direct FF connection)
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#
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# For an edge-aligned Source Synchronous interface, the clock
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# transition occurs at the same time as the data transitions.
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# In this template, the clock is aligned with the beginning of the
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# data. The constraints below rely on the default timing
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# analysis (setup = 1 cycle, hold = 0 cycle).
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#
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# input __________ ________________
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# clock |________________| |__________
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# |
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# skew_bre|skew_are
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# <------>|<------>
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# ________________ | ________________
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# data XXX________________XXXXXXXXXXXXXXXXX____Rise_Data___XXX
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#
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set input_clock <clock_name>; # Name of input clock
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set input_clock_period <period_value>; # Period of input clock
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set skew_bre 0.000; # Data invalid before the rising clock edge
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set skew_are 0.000; # Data invalid after the rising clock edge
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set input_ports <input_ports>; # List of input ports
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# Input Delay Constraint
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set_input_delay -clock $input_clock -max [expr $input_clock_period + $skew_are] [get_ports $input_ports];
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set_input_delay -clock $input_clock -min [expr $input_clock_period - $skew_bre] [get_ports $input_ports];
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# Report Timing Template
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# report_timing -from [get_ports $input_ports] -max_paths 20 -nworst 1 -delay_type min_max -name src_sync_edge_rise_in -file src_sync_edge_rise_in.txt;