时间基准电路和带使能的多周期计数器
module conter(
CLK , //xia jiang yan//CNTVAL, // 输出的计数值信号
OV );// 计数溢出信号,计数值为最大值时该信号为1
input CLK ;
//output [30:0] CNTVAL;
output OV;
//reg [30:0] CNTVAL ;
integer CNTVAL=0, a=0;
reg OV;
// 电路编译参数,最大计数值
parameter CNT_MAX_VAL = 5;
always @(posedge CLK) begin
if(CNTVAL < CNT_MAX_VAL)
begin // 未计数到最大值, 下一值加1
CNTVAL = CNTVAL + 1;
a=0;
end
else
begin// 计数到最大值,下一计数值为0
CNTVAL = 0;
a=1;
end
end
// 组合逻辑,生成OV
always @ (CLK) begin
if(a)
OV = 1;
else
OV = 0;
end
endmodule
实现0.0---9.9 0.1s一次 不断循环
module conter(
CLK , //xia jiang yan
//CNTVAL, // 输出的计数值信号
OV );// 计数溢出信号,计数值为最大值时该信号为1
input CLK ;
//output [30:0] CNTVAL;
output OV;
//reg [30:0] CNTVAL ;
integer CNTVAL=0, a=0;
reg OV;
// 电路编译参数,最大计数值
parameter CNT_MAX_VAL = 5;
always @(posedge CLK) begin
if(CNTVAL < CNT_MAX_VAL)
begin // 未计数到最大值, 下一值加1
CNTVAL = CNTVAL + 1;
a=0;
end
else
begin// 计数到最大值,下一计数值为0
CNTVAL = 0;
a=1;
end
end
// 组合逻辑,生成OV
always @ (CLK) begin
if(a)
OV = 1;
else
OV = 0;
end
endmodule
module enconter(
EN , //enable
CLK , //xia jiang yan
OUT0, // 输出的计数值信号 first
OUT1 , //output second
OV );// 计数溢出信号,计数值为最大值时该信号为1
input CLK,EN ;
output [7:0] OUT0;
output [7:0] OUT1 ;
output OV;
reg [3:0] CNTVAL ;
reg [7:0] OUT0 ;
reg [7:0] OUT1 ;
reg [3:0] a;
reg OV;
// 电路编译参数,最大计数值
parameter CNT_MAX_VAL = 10;
always @(posedge CLK) begin
if(EN)
begin
if(CNTVAL < CNT_MAX_VAL)
begin // 未计数到最大值, 下一值加1
CNTVAL = CNTVAL + 1'b1;
end
else
begin// 计数到最大值,下一计数值为0
CNTVAL = 0;
a= a+1'b1 ;
if(a == 10) begin
a= 0 ;
//CNTVAL = 0;
end
//else a =4'b0000;
end
end
//if(EN==0)
end
// 组合逻辑,生成OV
always @ (CLK) begin
if(CNTVAL==0)
OV = 1;
else
OV = 0;
end
always @ (CLK) begin
case(a)
4'b0000: begin OUT1 = 8'b 0100_0000;//0
case(CNTVAL)
4'b0000: OUT0 = 8'b 1100_0000;//0
4'b0001: OUT0 = 8'b 1111_1001;//1 0 bright
4'b0010: OUT0 = 8'b 1010_0100;//2
4'b0011: OUT0 = 8'b 1011_0000;//3
4'b0100: OUT0 = 8'b 1001_1001;//4
4'b0101: OUT0 = 8'b 1001_0010;//5
4'b0110: OUT0 = 8'b 1000_0010;//6
4'b0111: OUT0 = 8'b 1111_1000;//7
4'b1000: OUT0 = 8'b 1000_0000;//8
4'b1001: OUT0 = 8'b 1001_0000;//9
//4'b1010: OUT = 8'b 1000_1000;//A
//4'b1011: OUT = 8'b 1000_0011;//B
//4'b1100: OUT = 8'b 1010_0111;//c
//4'b1101: OUT = 8'b 1010_0001;//d
//4'b1110: OUT = 8'b 1000_0110;//e
//4'b1111: OUT = 8'b 1000_1110;//f
endcase
end
4'b0001: begin OUT1 = 8'b 0111_1001;//1
case(CNTVAL)
4'b0000: OUT0 = 8'b 1100_0000;//0
4'b0001: OUT0 = 8'b 1111_1001;//1 0 bright
4'b0010: OUT0 = 8'b 1010_0100;//2
4'b0011: OUT0 = 8'b 1011_0000;//3
4'b0100: OUT0 = 8'b 1001_1001;//4
4'b0101: OUT0 = 8'b 1001_0010;//5
4'b0110: OUT0 = 8'b 1000_0010;//6
4'b0111: OUT0 = 8'b 1111_1000;//7
4'b1000: OUT0 = 8'b 1000_0000;//8
4'b1001: OUT0 = 8'b 1001_0000;//9
//4'b1010: OUT = 8'b 1000_1000;//A
//4'b1011: OUT = 8'b 1000_0011;//B
//4'b1100: OUT = 8'b 1010_0111;//c
//4'b1101: OUT = 8'b 1010_0001;//d
//4'b1110: OUT = 8'b 1000_0110;//e
//4'b1111: OUT = 8'b 1000_1110;//f
endcase
end
4'b0010: begin OUT1 = 8'b 0010_0100;//2
case(CNTVAL)
4'b0000: OUT0 = 8'b 1100_0000;//0
4'b0001: OUT0 = 8'b 1111_1001;//1 0 bright
4'b0010: OUT0 = 8'b 1010_0100;//2
4'b0011: OUT0 = 8'b 1011_0000;//3
4'b0100: OUT0 = 8'b 1001_1001;//4
4'b0101: OUT0 = 8'b 1001_0010;//5
4'b0110: OUT0 = 8'b 1000_0010;//6
4'b0111: OUT0 = 8'b 1111_1000;//7
4'b1000: OUT0 = 8'b 1000_0000;//8
4'b1001: OUT0 = 8'b 1001_0000;//9
//4'b1010: OUT = 8'b 1000_1000;//A
//4'b1011: OUT = 8'b 1000_0011;//B
//4'b1100: OUT = 8'b 1010_0111;//c
//4'b1101: OUT = 8'b 1010_0001;//d
//4'b1110: OUT = 8'b 1000_0110;//e
//4'b1111: OUT = 8'b 1000_1110;//f
endcase
end
4'b0011: begin OUT1 = 8'b 0011_0000;//3
case(CNTVAL)
4'b0000: OUT0 = 8'b 1100_0000;//0
4'b0001: OUT0 = 8'b 1111_1001;//1 0 bright
4'b0010: OUT0 = 8'b 1010_0100;//2
4'b0011: OUT0 = 8'b 1011_0000;//3
4'b0100: OUT0 = 8'b 1001_1001;//4
4'b0101: OUT0 = 8'b 1001_0010;//5
4'b0110: OUT0 = 8'b 1000_0010;//6
4'b0111: OUT0 = 8'b 1111_1000;//7
4'b1000: OUT0 = 8'b 1000_0000;//8
4'b1001: OUT0 = 8'b 1001_0000;//9
//4'b1010: OUT = 8'b 1000_1000;//A
//4'b1011: OUT = 8'b 1000_0011;//B
//4'b1100: OUT = 8'b 1010_0111;//c
//4'b1101: OUT = 8'b 1010_0001;//d
//4'b1110: OUT = 8'b 1000_0110;//e
//4'b1111: OUT = 8'b 1000_1110;//f
endcase
end
4'b0100: begin OUT1 = 8'b 0001_1001;//4
case(CNTVAL)
4'b0000: OUT0 = 8'b 1100_0000;//0
4'b0001: OUT0 = 8'b 1111_1001;//1 0 bright
4'b0010: OUT0 = 8'b 1010_0100;//2
4'b0011: OUT0 = 8'b 1011_0000;//3
4'b0100: OUT0 = 8'b 1001_1001;//4
4'b0101: OUT0 = 8'b 1001_0010;//5
4'b0110: OUT0 = 8'b 1000_0010;//6
4'b0111: OUT0 = 8'b 1111_1000;//7
4'b1000: OUT0 = 8'b 1000_0000;//8
4'b1001: OUT0 = 8'b 1001_0000;//9
//4'b1010: OUT = 8'b 1000_1000;//A
//4'b1011: OUT = 8'b 1000_0011;//B
//4'b1100: OUT = 8'b 1010_0111;//c
//4'b1101: OUT = 8'b 1010_0001;//d
//4'b1110: OUT = 8'b 1000_0110;//e
//4'b1111: OUT = 8'b 1000_1110;//f
endcase
end
4'b0101: begin OUT1 = 8'b 0001_0010;//5
case(CNTVAL)
4'b0000: OUT0 = 8'b 1100_0000;//0
4'b0001: OUT0 = 8'b 1111_1001;//1 0 bright
4'b0010: OUT0 = 8'b 1010_0100;//2
4'b0011: OUT0 = 8'b 1011_0000;//3
4'b0100: OUT0 = 8'b 1001_1001;//4
4'b0101: OUT0 = 8'b 1001_0010;//5
4'b0110: OUT0 = 8'b 1000_0010;//6
4'b0111: OUT0 = 8'b 1111_1000;//7
4'b1000: OUT0 = 8'b 1000_0000;//8
4'b1001: OUT0 = 8'b 1001_0000;//9
//4'b1010: OUT = 8'b 1000_1000;//A
//4'b1011: OUT = 8'b 1000_0011;//B
//4'b1100: OUT = 8'b 1010_0111;//c
//4'b1101: OUT = 8'b 1010_0001;//d
//4'b1110: OUT = 8'b 1000_0110;//e
//4'b1111: OUT = 8'b 1000_1110;//f
endcase
end
4'b0110: begin OUT1 = 8'b 0000_0010;//6
case(CNTVAL)
4'b0000: OUT0 = 8'b 1100_0000;//0
4'b0001: OUT0 = 8'b 1111_1001;//1 0 bright
4'b0010: OUT0 = 8'b 1010_0100;//2
4'b0011: OUT0 = 8'b 1011_0000;//3
4'b0100: OUT0 = 8'b 1001_1001;//4
4'b0101: OUT0 = 8'b 1001_0010;//5
4'b0110: OUT0 = 8'b 1000_0010;//6
4'b0111: OUT0 = 8'b 1111_1000;//7
4'b1000: OUT0 = 8'b 1000_0000;//8
4'b1001: OUT0 = 8'b 1001_0000;//9
//4'b1010: OUT = 8'b 1000_1000;//A
//4'b1011: OUT = 8'b 1000_0011;//B
//4'b1100: OUT = 8'b 1010_0111;//c
//4'b1101: OUT = 8'b 1010_0001;//d
//4'b1110: OUT = 8'b 1000_0110;//e
//4'b1111: OUT = 8'b 1000_1110;//f
endcase
end
4'b0111: begin OUT1 = 8'b 0111_1000;//7
case(CNTVAL)
4'b0000: OUT0 = 8'b 1100_0000;//0
4'b0001: OUT0 = 8'b 1111_1001;//1 0 bright
4'b0010: OUT0 = 8'b 1010_0100;//2
4'b0011: OUT0 = 8'b 1011_0000;//3
4'b0100: OUT0 = 8'b 1001_1001;//4
4'b0101: OUT0 = 8'b 1001_0010;//5
4'b0110: OUT0 = 8'b 1000_0010;//6
4'b0111: OUT0 = 8'b 1111_1000;//7
4'b1000: OUT0 = 8'b 1000_0000;//8
4'b1001: OUT0 = 8'b 1001_0000;//9
//4'b1010: OUT = 8'b 1000_1000;//A
//4'b1011: OUT = 8'b 1000_0011;//B
//4'b1100: OUT = 8'b 1010_0111;//c
//4'b1101: OUT = 8'b 1010_0001;//d
//4'b1110: OUT = 8'b 1000_0110;//e
//4'b1111: OUT = 8'b 1000_1110;//f
endcase
end
4'b1000: begin OUT1 = 8'b 0000_0000;//8
case(CNTVAL)
4'b0000: OUT0 = 8'b 1100_0000;//0
4'b0001: OUT0 = 8'b 1111_1001;//1 0 bright
4'b0010: OUT0 = 8'b 1010_0100;//2
4'b0011: OUT0 = 8'b 1011_0000;//3
4'b0100: OUT0 = 8'b 1001_1001;//4
4'b0101: OUT0 = 8'b 1001_0010;//5
4'b0110: OUT0 = 8'b 1000_0010;//6
4'b0111: OUT0 = 8'b 1111_1000;//7
4'b1000: OUT0 = 8'b 1000_0000;//8
4'b1001: OUT0 = 8'b 1001_0000;//9
//4'b1010: OUT = 8'b 1000_1000;//A
//4'b1011: OUT = 8'b 1000_0011;//B
//4'b1100: OUT = 8'b 1010_0111;//c
//4'b1101: OUT = 8'b 1010_0001;//d
//4'b1110: OUT = 8'b 1000_0110;//e
//4'b1111: OUT = 8'b 1000_1110;//f
endcase
end
4'b1001: begin OUT1 = 8'b 0001_0000;//9
case(CNTVAL)
4'b0000: OUT0 = 8'b 1100_0000;//0
4'b0001: OUT0 = 8'b 1111_1001;//1 0 bright
4'b0010: OUT0 = 8'b 1010_0100;//2
4'b0011: OUT0 = 8'b 1011_0000;//3
4'b0100: OUT0 = 8'b 1001_1001;//4
4'b0101: OUT0 = 8'b 1001_0010;//5
4'b0110: OUT0 = 8'b 1000_0010;//6
4'b0111: OUT0 = 8'b 1111_1000;//7
4'b1000: OUT0 = 8'b 1000_0000;//8
4'b1001: OUT0 = 8'b 1001_0000;//9
//4'b1010: OUT = 8'b 1000_1000;//A
//4'b1011: OUT = 8'b 1000_0011;//B
//4'b1100: OUT = 8'b 1010_0111;//c
//4'b1101: OUT = 8'b 1010_0001;//d
//4'b1110: OUT = 8'b 1000_0110;//e
//4'b1111: OUT = 8'b 1000_1110;//f
endcase
end
endcase
end
endmodule
添加置零,暂停功能
实现不管暂停还是计数都可以清零。
像秒表一样
module conter(
CLK , //xia jiang yan
//CNTVAL, // 输出的计数值信号
OV );// 计数溢出信号,计数值为最大值时该信号为1
input CLK ;
//output [30:0] CNTVAL;
output OV;
//reg [30:0] CNTVAL ;
integer CNTVAL=0, a=0;
reg OV;
// 电路编译参数,最大计数值
parameter CNT_MAX_VAL = 5;
always @(posedge CLK) begin
if(CNTVAL < CNT_MAX_VAL)
begin // 未计数到最大值, 下一值加1
CNTVAL = CNTVAL + 1;
a=0;
end
else
begin// 计数到最大值,下一计数值为0
CNTVAL = 0;
a=1;
end
end
// 组合逻辑,生成OV
always @ (CLK) begin
if(a)
OV = 1;
else
OV = 0;
end
endmodule
module enconter(
EN , //enable
RD ,//set 0
CLK , //xia jiang yan
OUT0, // 输出的计数值信号 first
OUT1 , //output second
OV );// 计数溢出信号,计数值为最大值时该信号为1
input CLK,EN ,RD;
output [7:0] OUT0;
output [7:0] OUT1 ;
output OV;
reg [3:0] CNTVAL ;
reg [7:0] OUT0 ;
reg [7:0] OUT1 ;
reg [3:0] a;
reg OV;
// 电路编译参数,最大计数值
parameter CNT_MAX_VAL = 10;
always @(posedge CLK) begin
if(EN)
begin
if(CNTVAL < CNT_MAX_VAL)
begin // 未计数到最大值, 下一值加1
CNTVAL = CNTVAL + 1'b1;
end
else
begin// 计数到最大值,下一计数值为0
CNTVAL = 0;
a= a+1'b1 ;
if(a == 10) begin
a= 0 ;
//CNTVAL = 0;
end
//else a =4'b0000;
end
if(RD)
begin
a=4'b0000;
CNTVAL=4'b0000;
end
end
end
// 组合逻辑,生成OV
always @ (CLK) begin
if(CNTVAL==0)
OV = 1;
else
OV = 0;
end
always @ (CLK) begin
case(a)
4'b0000: begin OUT1 = 8'b 0100_0000;//0
case(CNTVAL)
4'b0000: OUT0 = 8'b 1100_0000;//0
4'b0001: OUT0 = 8'b 1111_1001;//1 0 bright
4'b0010: OUT0 = 8'b 1010_0100;//2
4'b0011: OUT0 = 8'b 1011_0000;//3
4'b0100: OUT0 = 8'b 1001_1001;//4
4'b0101: OUT0 = 8'b 1001_0010;//5
4'b0110: OUT0 = 8'b 1000_0010;//6
4'b0111: OUT0 = 8'b 1111_1000;//7
4'b1000: OUT0 = 8'b 1000_0000;//8
4'b1001: OUT0 = 8'b 1001_0000;//9
//4'b1010: OUT = 8'b 1000_1000;//A
//4'b1011: OUT = 8'b 1000_0011;//B
//4'b1100: OUT = 8'b 1010_0111;//c
//4'b1101: OUT = 8'b 1010_0001;//d
//4'b1110: OUT = 8'b 1000_0110;//e
//4'b1111: OUT = 8'b 1000_1110;//f
endcase
end
4'b0001: begin OUT1 = 8'b 0111_1001;//1
case(CNTVAL)
4'b0000: OUT0 = 8'b 1100_0000;//0
4'b0001: OUT0 = 8'b 1111_1001;//1 0 bright
4'b0010: OUT0 = 8'b 1010_0100;//2
4'b0011: OUT0 = 8'b 1011_0000;//3
4'b0100: OUT0 = 8'b 1001_1001;//4
4'b0101: OUT0 = 8'b 1001_0010;//5
4'b0110: OUT0 = 8'b 1000_0010;//6
4'b0111: OUT0 = 8'b 1111_1000;//7
4'b1000: OUT0 = 8'b 1000_0000;//8
4'b1001: OUT0 = 8'b 1001_0000;//9
//4'b1010: OUT = 8'b 1000_1000;//A
//4'b1011: OUT = 8'b 1000_0011;//B
//4'b1100: OUT = 8'b 1010_0111;//c
//4'b1101: OUT = 8'b 1010_0001;//d
//4'b1110: OUT = 8'b 1000_0110;//e
//4'b1111: OUT = 8'b 1000_1110;//f
endcase
end
4'b0010: begin OUT1 = 8'b 0010_0100;//2
case(CNTVAL)
4'b0000: OUT0 = 8'b 1100_0000;//0
4'b0001: OUT0 = 8'b 1111_1001;//1 0 bright
4'b0010: OUT0 = 8'b 1010_0100;//2
4'b0011: OUT0 = 8'b 1011_0000;//3
4'b0100: OUT0 = 8'b 1001_1001;//4
4'b0101: OUT0 = 8'b 1001_0010;//5
4'b0110: OUT0 = 8'b 1000_0010;//6
4'b0111: OUT0 = 8'b 1111_1000;//7
4'b1000: OUT0 = 8'b 1000_0000;//8
4'b1001: OUT0 = 8'b 1001_0000;//9
//4'b1010: OUT = 8'b 1000_1000;//A
//4'b1011: OUT = 8'b 1000_0011;//B
//4'b1100: OUT = 8'b 1010_0111;//c
//4'b1101: OUT = 8'b 1010_0001;//d
//4'b1110: OUT = 8'b 1000_0110;//e
//4'b1111: OUT = 8'b 1000_1110;//f
endcase
end
4'b0011: begin OUT1 = 8'b 0011_0000;//3
case(CNTVAL)
4'b0000: OUT0 = 8'b 1100_0000;//0
4'b0001: OUT0 = 8'b 1111_1001;//1 0 bright
4'b0010: OUT0 = 8'b 1010_0100;//2
4'b0011: OUT0 = 8'b 1011_0000;//3
4'b0100: OUT0 = 8'b 1001_1001;//4
4'b0101: OUT0 = 8'b 1001_0010;//5
4'b0110: OUT0 = 8'b 1000_0010;//6
4'b0111: OUT0 = 8'b 1111_1000;//7
4'b1000: OUT0 = 8'b 1000_0000;//8
4'b1001: OUT0 = 8'b 1001_0000;//9
//4'b1010: OUT = 8'b 1000_1000;//A
//4'b1011: OUT = 8'b 1000_0011;//B
//4'b1100: OUT = 8'b 1010_0111;//c
//4'b1101: OUT = 8'b 1010_0001;//d
//4'b1110: OUT = 8'b 1000_0110;//e
//4'b1111: OUT = 8'b 1000_1110;//f
endcase
end
4'b0100: begin OUT1 = 8'b 0001_1001;//4
case(CNTVAL)
4'b0000: OUT0 = 8'b 1100_0000;//0
4'b0001: OUT0 = 8'b 1111_1001;//1 0 bright
4'b0010: OUT0 = 8'b 1010_0100;//2
4'b0011: OUT0 = 8'b 1011_0000;//3
4'b0100: OUT0 = 8'b 1001_1001;//4
4'b0101: OUT0 = 8'b 1001_0010;//5
4'b0110: OUT0 = 8'b 1000_0010;//6
4'b0111: OUT0 = 8'b 1111_1000;//7
4'b1000: OUT0 = 8'b 1000_0000;//8
4'b1001: OUT0 = 8'b 1001_0000;//9
//4'b1010: OUT = 8'b 1000_1000;//A
//4'b1011: OUT = 8'b 1000_0011;//B
//4'b1100: OUT = 8'b 1010_0111;//c
//4'b1101: OUT = 8'b 1010_0001;//d
//4'b1110: OUT = 8'b 1000_0110;//e
//4'b1111: OUT = 8'b 1000_1110;//f
endcase
end
4'b0101: begin OUT1 = 8'b 0001_0010;//5
case(CNTVAL)
4'b0000: OUT0 = 8'b 1100_0000;//0
4'b0001: OUT0 = 8'b 1111_1001;//1 0 bright
4'b0010: OUT0 = 8'b 1010_0100;//2
4'b0011: OUT0 = 8'b 1011_0000;//3
4'b0100: OUT0 = 8'b 1001_1001;//4
4'b0101: OUT0 = 8'b 1001_0010;//5
4'b0110: OUT0 = 8'b 1000_0010;//6
4'b0111: OUT0 = 8'b 1111_1000;//7
4'b1000: OUT0 = 8'b 1000_0000;//8
4'b1001: OUT0 = 8'b 1001_0000;//9
//4'b1010: OUT = 8'b 1000_1000;//A
//4'b1011: OUT = 8'b 1000_0011;//B
//4'b1100: OUT = 8'b 1010_0111;//c
//4'b1101: OUT = 8'b 1010_0001;//d
//4'b1110: OUT = 8'b 1000_0110;//e
//4'b1111: OUT = 8'b 1000_1110;//f
endcase
end
4'b0110: begin OUT1 = 8'b 0000_0010;//6
case(CNTVAL)
4'b0000: OUT0 = 8'b 1100_0000;//0
4'b0001: OUT0 = 8'b 1111_1001;//1 0 bright
4'b0010: OUT0 = 8'b 1010_0100;//2
4'b0011: OUT0 = 8'b 1011_0000;//3
4'b0100: OUT0 = 8'b 1001_1001;//4
4'b0101: OUT0 = 8'b 1001_0010;//5
4'b0110: OUT0 = 8'b 1000_0010;//6
4'b0111: OUT0 = 8'b 1111_1000;//7
4'b1000: OUT0 = 8'b 1000_0000;//8
4'b1001: OUT0 = 8'b 1001_0000;//9
//4'b1010: OUT = 8'b 1000_1000;//A
//4'b1011: OUT = 8'b 1000_0011;//B
//4'b1100: OUT = 8'b 1010_0111;//c
//4'b1101: OUT = 8'b 1010_0001;//d
//4'b1110: OUT = 8'b 1000_0110;//e
//4'b1111: OUT = 8'b 1000_1110;//f
endcase
end
4'b0111: begin OUT1 = 8'b 0111_1000;//7
case(CNTVAL)
4'b0000: OUT0 = 8'b 1100_0000;//0
4'b0001: OUT0 = 8'b 1111_1001;//1 0 bright
4'b0010: OUT0 = 8'b 1010_0100;//2
4'b0011: OUT0 = 8'b 1011_0000;//3
4'b0100: OUT0 = 8'b 1001_1001;//4
4'b0101: OUT0 = 8'b 1001_0010;//5
4'b0110: OUT0 = 8'b 1000_0010;//6
4'b0111: OUT0 = 8'b 1111_1000;//7
4'b1000: OUT0 = 8'b 1000_0000;//8
4'b1001: OUT0 = 8'b 1001_0000;//9
//4'b1010: OUT = 8'b 1000_1000;//A
//4'b1011: OUT = 8'b 1000_0011;//B
//4'b1100: OUT = 8'b 1010_0111;//c
//4'b1101: OUT = 8'b 1010_0001;//d
//4'b1110: OUT = 8'b 1000_0110;//e
//4'b1111: OUT = 8'b 1000_1110;//f
endcase
end
4'b1000: begin OUT1 = 8'b 0000_0000;//8
case(CNTVAL)
4'b0000: OUT0 = 8'b 1100_0000;//0
4'b0001: OUT0 = 8'b 1111_1001;//1 0 bright
4'b0010: OUT0 = 8'b 1010_0100;//2
4'b0011: OUT0 = 8'b 1011_0000;//3
4'b0100: OUT0 = 8'b 1001_1001;//4
4'b0101: OUT0 = 8'b 1001_0010;//5
4'b0110: OUT0 = 8'b 1000_0010;//6
4'b0111: OUT0 = 8'b 1111_1000;//7
4'b1000: OUT0 = 8'b 1000_0000;//8
4'b1001: OUT0 = 8'b 1001_0000;//9
//4'b1010: OUT = 8'b 1000_1000;//A
//4'b1011: OUT = 8'b 1000_0011;//B
//4'b1100: OUT = 8'b 1010_0111;//c
//4'b1101: OUT = 8'b 1010_0001;//d
//4'b1110: OUT = 8'b 1000_0110;//e
//4'b1111: OUT = 8'b 1000_1110;//f
endcase
end
4'b1001: begin OUT1 = 8'b 0001_0000;//9
case(CNTVAL)
4'b0000: OUT0 = 8'b 1100_0000;//0
4'b0001: OUT0 = 8'b 1111_1001;//1 0 bright
4'b0010: OUT0 = 8'b 1010_0100;//2
4'b0011: OUT0 = 8'b 1011_0000;//3
4'b0100: OUT0 = 8'b 1001_1001;//4
4'b0101: OUT0 = 8'b 1001_0010;//5
4'b0110: OUT0 = 8'b 1000_0010;//6
4'b0111: OUT0 = 8'b 1111_1000;//7
4'b1000: OUT0 = 8'b 1000_0000;//8
4'b1001: OUT0 = 8'b 1001_0000;//9
//4'b1010: OUT = 8'b 1000_1000;//A
//4'b1011: OUT = 8'b 1000_0011;//B
//4'b1100: OUT = 8'b 1010_0111;//c
//4'b1101: OUT = 8'b 1010_0001;//d
//4'b1110: OUT = 8'b 1000_0110;//e
//4'b1111: OUT = 8'b 1000_1110;//f
endcase
end
endcase
end
//always @ (CLK) begin
//if(RD)
////begin
//OUT1 = 8'b 0100_0000;
//OUT0 = 8'b 1100_0000;
//end
//end
//always @ (CLK) begin
//if(P==0)
// EN=0;
//end
endmodule