第二篇:mig IP的创建
FPGA开源工作室将通过五篇文章来给大家讲解xilinx FPGA 使用mig IP对DDR3的读写控制,旨在让大家更快的学习和应用DDR3。
本实验和工程基于Digilent的Arty Artix-35T FPGA开发板完成。
软件使用Vivado 2018.1
第二篇:mig IP的创建
1 DDR3
Digilent的Arty Artix-35T FPGA开发板板载MT41K128M16JT-125 DDR3基本信息如下表所示。
2 mig IP的创建
1>点击IP Catalog ->搜索mig->双击Memory Interface Generator(MIG 7 Series)
2>打开后可以看到一些基本信息
- 3>Enter a component name in the Component Name field ->Next
Component name(组件名称):ddr3_ip
4>这里我们不做兼容性选择,直接下一步
5>控制类型选择DDR3 SDRAM
- ①Clock Period:(此功能表示所有控制器的工作频率,频率模块受所选FPGA和器件速度等级等因素的限制。) 3000ps(333.33MHZ)。
②PHY to Controller Clock Ratio :(此功能确定物理层(存储器)时钟频率与控制器和用户界面时钟频率的比率。 由于FPGA逻辑时序限制,2:1比率会降低最大存储器接口频率。 2:1比率的用户界面数据总线宽度是物理存储器接口宽度宽度的四倍,而4:1比率的总线宽度是物理存储器接口宽度的八倍。 2:1比率具有较低的延迟。 4:1的比率是最高数据速率所必需的)4:1。
③Memory Type:此功能选择设计中使用的内存部件类型。
④Memory Part :此选项为设计选择内存部件。 选择可以从列表中创建或者可以创建新部件。MT41K128M16XX-15E。
⑤Memory Voltage:根据设计原理图1.35V。
⑥Data Width:(可以根据之前选择的存储器类型在此处选择数据宽度值。 该列表显示所选部件的所有支持的数据宽度。 可以选择其中一个数据宽度。 这些值通常是各个器件数据宽度的倍数。 在某些情况下,宽度可能不是精确倍数。 例如,16位是x16组件的默认数据宽度,但8位也是有效值。)16。
⑦Data Mask:(选择时,此选项会分配数据屏蔽引脚。 应取消选择此选项以释放数据屏蔽引脚并提高引脚效率。 此外,对于不支持数据掩码的内存部分禁用此功能。)勾选。
NXET。
- ①Input clock Period:6000ps(166.667MHZ)。
②Read Burst Type and Length:Sequential。
③Output Driver Impedance Control:RZQ/6。
其他默认,NEXT。
- ①System Clock :(此选项为sys_clk信号对选择时钟类型(单端,差分或无缓冲)。 选择No Buffer选项时,IBUF原语不会在RTL代码中实例化,并且不会为系统时钟分配引脚。 )No Buffer。
②Reference Clock :(此选项为clk_ref信号对选择时钟类型(单端,差分,无缓冲或使用系统时钟)。 当输入频率介于199和201 MHz之间时(即输入时钟周期介于5,025 ps(199 MHz)和4,975 ps(201 MHz)之间),将显示Use System Clock(使用系统时钟)选项。参考时钟频率基于数据速率 并注意添加MMCM以创建高于1,333 Mb / s的适当ref_clk频率。当选择No Buffer选项时,IBUF原语不会在RTL代码中实例化,并且引脚不会分配给参考时钟。)No Buffer。
③System Reset Polarity:(可以选择系统复位(sys_rst)的极性。 如果选项选择为低电平有效,则参数RST_ACT_LOW设置为1,如果设置为高电平 - 高,则参数RST_ACT_LOW设置为0。)ACTIVE LOW。
④Debug Signals Control:选择此选项可以将校准状态和用户端口信号端口映射到example_top模块中的ILA和VIO。 这有助于使用Vivado Design Suite调试功能监控用户界面端口上的流量。 取消选择Debug Signals Control选项会使example_top模块中的调试信号保持未连接状态,并且IP目录不会生成ILA / VIO模块。 此外,始终禁用调试端口以进行功能仿真。OFF。
⑤Sample Data Depth:此选项选择Vivado调试逻辑中使用的ILA模块的样本数据深度。 当“内存控制器的调试信号”选项为“开”时,可以选择此选项。
⑥Internal Verf:(内部VREF可用于数据组字节,以允许使用VREF引脚进行正常的I / O使用。 内部VREF仅应用于800 Mb / s或更低的数据速率。)勾选。
其他默认,NEXT。
- 默认,NEXT。
10>选择Fixed Pin Out。我们的原理图管脚已经确定无需从新设计。
- 点击Read XDC/UCF,这里DDR3管脚支持两种约束文件。
UCF:
XDC:
- ##################################################################################################
- ##
- ## Xilinx, Inc. 2010 www.xilinx.com
- ## 周五 一月 25 13:58:27 2019
- ## Generated by MIG Version 2.4
- ##
- ##################################################################################################
- ## File name : ddr3_ip.xdc
- ## Details : Constraints file
- ## FPGA Family: ARTIX7
- ## FPGA Part: XC7A35TI-CSG324
- ## Speedgrade: -1L
- ## Design Entry: VERILOG
- ## Frequency: 333.333 MHz
- ## Time Period: 3000 ps
- ##################################################################################################
- ##################################################################################################
- ## Controller 0
- ## Memory Device: DDR3_SDRAM->Components->MT41K128M16XX-15E
- ## Data Width: 16
- ## Time Period: 3000
- ## Data Mask: 1
- ##################################################################################################
- #create_clock -period 6 [get_ports sys_clk_i]
- #create_clock -period 5 [get_ports clk_ref_i]
- ############## NET - IOSTANDARD ##################
- # PadFunction: IO_L5P_T0_34
- set_property SLEW FAST [get_ports {ddr3_dq[0]}]
- set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[0]}]
- set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[0]}]
- set_property PACKAGE_PIN K5 [get_ports {ddr3_dq[0]}]
- # PadFunction: IO_L2N_T0_34
- set_property SLEW FAST [get_ports {ddr3_dq[1]}]
- set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[1]}]
- set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[1]}]
- set_property PACKAGE_PIN L3 [get_ports {ddr3_dq[1]}]
- # PadFunction: IO_L2P_T0_34
- set_property SLEW FAST [get_ports {ddr3_dq[2]}]
- set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[2]}]
- set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[2]}]
- set_property PACKAGE_PIN K3 [get_ports {ddr3_dq[2]}]
- # PadFunction: IO_L6P_T0_34
- set_property SLEW FAST [get_ports {ddr3_dq[3]}]
- set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[3]}]
- set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[3]}]
- set_property PACKAGE_PIN L6 [get_ports {ddr3_dq[3]}]
- # PadFunction: IO_L4P_T0_34
- set_property SLEW FAST [get_ports {ddr3_dq[4]}]
- set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[4]}]
- set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[4]}]
- set_property PACKAGE_PIN M3 [get_ports {ddr3_dq[4]}]
- # PadFunction: IO_L1N_T0_34
- set_property SLEW FAST [get_ports {ddr3_dq[5]}]
- set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[5]}]
- set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[5]}]
- set_property PACKAGE_PIN M1 [get_ports {ddr3_dq[5]}]
- # PadFunction: IO_L5N_T0_34
- set_property SLEW FAST [get_ports {ddr3_dq[6]}]
- set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[6]}]
- set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[6]}]
- set_property PACKAGE_PIN L4 [get_ports {ddr3_dq[6]}]
- # PadFunction: IO_L4N_T0_34
- set_property SLEW FAST [get_ports {ddr3_dq[7]}]
- set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[7]}]
- set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[7]}]
- set_property PACKAGE_PIN M2 [get_ports {ddr3_dq[7]}]
- # PadFunction: IO_L10N_T1_34
- set_property SLEW FAST [get_ports {ddr3_dq[8]}]
- set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[8]}]
- set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[8]}]
- set_property PACKAGE_PIN V4 [get_ports {ddr3_dq[8]}]
- # PadFunction: IO_L12P_T1_MRCC_34
- set_property SLEW FAST [get_ports {ddr3_dq[9]}]
- set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[9]}]
- set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[9]}]
- set_property PACKAGE_PIN T5 [get_ports {ddr3_dq[9]}]
- # PadFunction: IO_L8P_T1_34
- set_property SLEW FAST [get_ports {ddr3_dq[10]}]
- set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[10]}]
- set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[10]}]
- set_property PACKAGE_PIN U4 [get_ports {ddr3_dq[10]}]
- # PadFunction: IO_L10P_T1_34
- set_property SLEW FAST [get_ports {ddr3_dq[11]}]
- set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[11]}]
- set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[11]}]
- set_property PACKAGE_PIN V5 [get_ports {ddr3_dq[11]}]
- # PadFunction: IO_L7N_T1_34
- set_property SLEW FAST [get_ports {ddr3_dq[12]}]
- set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[12]}]
- set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[12]}]
- set_property PACKAGE_PIN V1 [get_ports {ddr3_dq[12]}]
- # PadFunction: IO_L11N_T1_SRCC_34
- set_property SLEW FAST [get_ports {ddr3_dq[13]}]
- set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[13]}]
- set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[13]}]
- set_property PACKAGE_PIN T3 [get_ports {ddr3_dq[13]}]
- # PadFunction: IO_L8N_T1_34
- set_property SLEW FAST [get_ports {ddr3_dq[14]}]
- set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[14]}]
- set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[14]}]
- set_property PACKAGE_PIN U3 [get_ports {ddr3_dq[14]}]
- # PadFunction: IO_L11P_T1_SRCC_34
- set_property SLEW FAST [get_ports {ddr3_dq[15]}]
- set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[15]}]
- set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[15]}]
- set_property PACKAGE_PIN R3 [get_ports {ddr3_dq[15]}]
- # PadFunction: IO_L24N_T3_34
- set_property SLEW FAST [get_ports {ddr3_addr[13]}]
- set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[13]}]
- set_property PACKAGE_PIN T8 [get_ports {ddr3_addr[13]}]
- # PadFunction: IO_L23N_T3_34
- set_property SLEW FAST [get_ports {ddr3_addr[12]}]
- set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[12]}]
- set_property PACKAGE_PIN T6 [get_ports {ddr3_addr[12]}]
- # PadFunction: IO_L22N_T3_34
- set_property SLEW FAST [get_ports {ddr3_addr[11]}]
- set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[11]}]
- set_property PACKAGE_PIN U6 [get_ports {ddr3_addr[11]}]
- # PadFunction: IO_L19P_T3_34
- set_property SLEW FAST [get_ports {ddr3_addr[10]}]
- set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[10]}]
- set_property PACKAGE_PIN R6 [get_ports {ddr3_addr[10]}]
- # PadFunction: IO_L20P_T3_34
- set_property SLEW FAST [get_ports {ddr3_addr[9]}]
- set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[9]}]
- set_property PACKAGE_PIN V7 [get_ports {ddr3_addr[9]}]
- # PadFunction: IO_L24P_T3_34
- set_property SLEW FAST [get_ports {ddr3_addr[8]}]
- set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[8]}]
- set_property PACKAGE_PIN R8 [get_ports {ddr3_addr[8]}]
- # PadFunction: IO_L22P_T3_34
- set_property SLEW FAST [get_ports {ddr3_addr[7]}]
- set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[7]}]
- set_property PACKAGE_PIN U7 [get_ports {ddr3_addr[7]}]
- # PadFunction: IO_L20N_T3_34
- set_property SLEW FAST [get_ports {ddr3_addr[6]}]
- set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[6]}]
- set_property PACKAGE_PIN V6 [get_ports {ddr3_addr[6]}]
- # PadFunction: IO_L23P_T3_34
- set_property SLEW FAST [get_ports {ddr3_addr[5]}]
- set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[5]}]
- set_property PACKAGE_PIN R7 [get_ports {ddr3_addr[5]}]
- # PadFunction: IO_L18N_T2_34
- set_property SLEW FAST [get_ports {ddr3_addr[4]}]
- set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[4]}]
- set_property PACKAGE_PIN N6 [get_ports {ddr3_addr[4]}]
- # PadFunction: IO_L17N_T2_34
- set_property SLEW FAST [get_ports {ddr3_addr[3]}]
- set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[3]}]
- set_property PACKAGE_PIN T1 [get_ports {ddr3_addr[3]}]
- # PadFunction: IO_L16N_T2_34
- set_property SLEW FAST [get_ports {ddr3_addr[2]}]
- set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[2]}]
- set_property PACKAGE_PIN N4 [get_ports {ddr3_addr[2]}]
- # PadFunction: IO_L18P_T2_34
- set_property SLEW FAST [get_ports {ddr3_addr[1]}]
- set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[1]}]
- set_property PACKAGE_PIN M6 [get_ports {ddr3_addr[1]}]
- # PadFunction: IO_L15N_T2_DQS_34
- set_property SLEW FAST [get_ports {ddr3_addr[0]}]
- set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[0]}]
- set_property PACKAGE_PIN R2 [get_ports {ddr3_addr[0]}]
- # PadFunction: IO_L15P_T2_DQS_34
- set_property SLEW FAST [get_ports {ddr3_ba[2]}]
- set_property IOSTANDARD SSTL135 [get_ports {ddr3_ba[2]}]
- set_property PACKAGE_PIN P2 [get_ports {ddr3_ba[2]}]
- # PadFunction: IO_L14P_T2_SRCC_34
- set_property SLEW FAST [get_ports {ddr3_ba[1]}]
- set_property IOSTANDARD SSTL135 [get_ports {ddr3_ba[1]}]
- set_property PACKAGE_PIN P4 [get_ports {ddr3_ba[1]}]
- # PadFunction: IO_L17P_T2_34
- set_property SLEW FAST [get_ports {ddr3_ba[0]}]
- set_property IOSTANDARD SSTL135 [get_ports {ddr3_ba[0]}]
- set_property PACKAGE_PIN R1 [get_ports {ddr3_ba[0]}]
- # PadFunction: IO_L14N_T2_SRCC_34
- set_property SLEW FAST [get_ports {ddr3_ras_n}]
- set_property IOSTANDARD SSTL135 [get_ports {ddr3_ras_n}]
- set_property PACKAGE_PIN P3 [get_ports {ddr3_ras_n}]
- # PadFunction: IO_L16P_T2_34
- set_property SLEW FAST [get_ports {ddr3_cas_n}]
- set_property IOSTANDARD SSTL135 [get_ports {ddr3_cas_n}]
- set_property PACKAGE_PIN M4 [get_ports {ddr3_cas_n}]
- # PadFunction: IO_L13N_T2_MRCC_34
- set_property SLEW FAST [get_ports {ddr3_we_n}]
- set_property IOSTANDARD SSTL135 [get_ports {ddr3_we_n}]
- set_property PACKAGE_PIN P5 [get_ports {ddr3_we_n}]
- # PadFunction: IO_0_34
- set_property SLEW FAST [get_ports {ddr3_reset_n}]
- set_property IOSTANDARD SSTL135 [get_ports {ddr3_reset_n}]
- set_property PACKAGE_PIN K6 [get_ports {ddr3_reset_n}]
- # PadFunction: IO_L13P_T2_MRCC_34
- set_property SLEW FAST [get_ports {ddr3_cke[0]}]
- set_property IOSTANDARD SSTL135 [get_ports {ddr3_cke[0]}]
- set_property PACKAGE_PIN N5 [get_ports {ddr3_cke[0]}]
- # PadFunction: IO_L19N_T3_VREF_34
- set_property SLEW FAST [get_ports {ddr3_odt[0]}]
- set_property IOSTANDARD SSTL135 [get_ports {ddr3_odt[0]}]
- set_property PACKAGE_PIN R5 [get_ports {ddr3_odt[0]}]
- # PadFunction: IO_25_34
- set_property SLEW FAST [get_ports {ddr3_cs_n[0]}]
- set_property IOSTANDARD SSTL135 [get_ports {ddr3_cs_n[0]}]
- set_property PACKAGE_PIN U8 [get_ports {ddr3_cs_n[0]}]
- # PadFunction: IO_L1P_T0_34
- set_property SLEW FAST [get_ports {ddr3_dm[0]}]
- set_property IOSTANDARD SSTL135 [get_ports {ddr3_dm[0]}]
- set_property PACKAGE_PIN L1 [get_ports {ddr3_dm[0]}]
- # PadFunction: IO_L7P_T1_34
- set_property SLEW FAST [get_ports {ddr3_dm[1]}]
- set_property IOSTANDARD SSTL135 [get_ports {ddr3_dm[1]}]
- set_property PACKAGE_PIN U1 [get_ports {ddr3_dm[1]}]
- # PadFunction: IO_L3P_T0_DQS_34
- set_property SLEW FAST [get_ports {ddr3_dqs_p[0]}]
- set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dqs_p[0]}]
- set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddr3_dqs_p[0]}]
- set_property PACKAGE_PIN N2 [get_ports {ddr3_dqs_p[0]}]
- # PadFunction: IO_L3N_T0_DQS_34
- set_property SLEW FAST [get_ports {ddr3_dqs_n[0]}]
- set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dqs_n[0]}]
- set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddr3_dqs_n[0]}]
- set_property PACKAGE_PIN N1 [get_ports {ddr3_dqs_n[0]}]
- # PadFunction: IO_L9P_T1_DQS_34
- set_property SLEW FAST [get_ports {ddr3_dqs_p[1]}]
- set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dqs_p[1]}]
- set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddr3_dqs_p[1]}]
- set_property PACKAGE_PIN U2 [get_ports {ddr3_dqs_p[1]}]
- # PadFunction: IO_L9N_T1_DQS_34
- set_property SLEW FAST [get_ports {ddr3_dqs_n[1]}]
- set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dqs_n[1]}]
- set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddr3_dqs_n[1]}]
- set_property PACKAGE_PIN V2 [get_ports {ddr3_dqs_n[1]}]
- # PadFunction: IO_L21P_T3_DQS_34
- set_property SLEW FAST [get_ports {ddr3_ck_p[0]}]
- set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddr3_ck_p[0]}]
- set_property PACKAGE_PIN U9 [get_ports {ddr3_ck_p[0]}]
- # PadFunction: IO_L21N_T3_DQS_34
- set_property SLEW FAST [get_ports {ddr3_ck_n[0]}]
- set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddr3_ck_n[0]}]
- set_property PACKAGE_PIN V9 [get_ports {ddr3_ck_n[0]}]
- set_property INTERNAL_VREF 0.675 [get_iobanks 34]
- set_property LOC PHASER_OUT_PHY_X1Y1 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out}]
- set_property LOC PHASER_OUT_PHY_X1Y0 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out}]
- set_property LOC PHASER_OUT_PHY_X1Y3 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out}]
- set_property LOC PHASER_OUT_PHY_X1Y2 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out}]
- ## set_property LOC PHASER_IN_PHY_X1Y1 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_in_gen.phaser_in}]
- ## set_property LOC PHASER_IN_PHY_X1Y0 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_in_gen.phaser_in}]
- set_property LOC PHASER_IN_PHY_X1Y3 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in}]
- set_property LOC PHASER_IN_PHY_X1Y2 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in}]
- set_property LOC OUT_FIFO_X1Y1 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo}]
- set_property LOC OUT_FIFO_X1Y0 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo}]
- set_property LOC OUT_FIFO_X1Y3 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo}]
- set_property LOC OUT_FIFO_X1Y2 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo}]
- set_property LOC IN_FIFO_X1Y3 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo}]
- set_property LOC IN_FIFO_X1Y2 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo}]
- set_property LOC PHY_CONTROL_X1Y0 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i}]
- set_property LOC PHASER_REF_X1Y0 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/phaser_ref_i}]
- set_property LOC OLOGIC_X1Y43 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/*slave_ts}]
- set_property LOC OLOGIC_X1Y31 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/*slave_ts}]
- set_property LOC PLLE2_ADV_X1Y0 [get_cells -hier -filter {NAME =~ */u_ddr3_infrastructure/plle2_i}]
- set_property LOC MMCME2_ADV_X1Y0 [get_cells -hier -filter {NAME =~ */u_ddr3_infrastructure/gen_mmcm.mmcm_i}]
- set_multicycle_path -from [get_cells -hier -filter {NAME =~ */mc0/mc_read_idle_r_reg}] \
- -to [get_cells -hier -filter {NAME =~ */input_[?].iserdes_dq_.iserdesdq}] \
- -setup 6
- set_multicycle_path -from [get_cells -hier -filter {NAME =~ */mc0/mc_read_idle_r_reg}] \
- -to [get_cells -hier -filter {NAME =~ */input_[?].iserdes_dq_.iserdesdq}] \
- -hold 5
- set_false_path -through [get_pins -filter {NAME =~ */DQSFOUND} -of [get_cells -hier -filter {REF_NAME == PHASER_IN_PHY}]]
- set_multicycle_path -through [get_pins -filter {NAME =~ */OSERDESRST} -of [get_cells -hier -filter {REF_NAME == PHASER_OUT_PHY}]] -setup 2 -start
- set_multicycle_path -through [get_pins -filter {NAME =~ */OSERDESRST} -of [get_cells -hier -filter {REF_NAME == PHASER_OUT_PHY}]] -hold 1 -start
- set_max_delay -datapath_only -from [get_cells -hier -filter {NAME =~ *temp_mon_enabled.u_tempmon/* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {NAME =~ *temp_mon_enabled.u_tempmon/device_temp_sync_r1*}] 20
- set_max_delay -from [get_cells -hier *rstdiv0_sync_r1_reg*] -to [get_pins -filter {NAME =~ */RESET} -of [get_cells -hier -filter {REF_NAME == PHY_CONTROL}]] -datapath_only 5
- set_false_path -through [get_pins -hier -filter {NAME =~ */u_iodelay_ctrl/sys_rst}]
- set_max_delay -datapath_only -from [get_cells -hier -filter {NAME =~ *ddr3_infrastructure/rstdiv0_sync_r1_reg*}] -to [get_cells -hier -filter {NAME =~ *temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r1*}] 20
12>点击Validate验证管脚约束是否有错误。验证通过NEXT。
- 默认,NEXT。
14>Next。
15>Accept,Next。
16>Generate
17>Generate
18>至此我们的mig IP创建完成。
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