Techniques to make clock switching glitch free（FPGA时钟切换无毛刺技术）

With more and more multi-frequency clocks being used in today's chips, especially in the communications field, it is often necessary to switch the source of a clock line while the chip is running. This is usually implemented by multiplexing two different frequency clock sources in hardware and controlling the multiplexer select line by internal logic.

随着越来越多的多频时钟被应用在今天的芯片中，尤其是在通信领域中，经常需要在芯片运行时切换时钟线的源时钟。这通常是通过在硬件中复用两个不同的频率时钟源，并通过内部逻辑控制多路选择器选择线来实现的。

The two clock frequencies could be totally unrelated to each other or they may be multiples of each other. In either case, there is a chance of generating a glitch on the clock line at the time of the switch. A glitch on the clock line is hazardous to the whole system, as it could be interpreted as a capture clock edge by some registers while missed by others.

这两个时钟频率可能彼此完全无关联（如时钟相位，频率之间的关系），或者它们可以是彼此之间存在倍数的关系。在这两种情况下，都有可能在开关时在时钟线上产生毛刺（glitch）。时钟线上的毛刺对整个系统来说是危险的，因为它可以被一些寄存器解释为捕获时钟边缘（寄存器对时钟也存在类似于对数据建立保持关系的要求，如果这个毛刺的高电平时间满足了某些寄存器对时钟边沿检测的要求，假定触发器上升沿捕获数据，即可触发寄存器捕获数据，这并不意味着对时钟一定要是50%的占空比，个人推测理解），而其他寄存器则忽略此毛刺（整个系统数据出现混乱）。

In this article, two different methods of avoiding a glitch at the output clock line of a switch are presented. The first method is used when clocks are multiples of each other, while the second deals with clocks totally unrelated to each other.

在这篇文章中，两种不同的方法避免故障在开关的输出时钟线。第一种方法是在两个时钟存在相互倍数关系的情况下使用的，而第二种方法处理的时钟完全互不相关。

The problem with on-the-fly clock switching

 

Figure 1 shows a simple implementation of a clock switch, using an AND-OR type multiplexer logic.

图1显示了一个使用AND或OR型多路复用器逻辑的时钟开关的简单实现。

The multiplexer has one control signal, named SELECT, which either propagates CLK0 to the output when set to "zero" or propagates CLK1 to the output when set to "one." A glitch may be caused due to immediate switching of the output from Current Clock source to the Next Clock source, when the SELECT value changes. Current Clock is the clock source currently selected while Next Clock is the clock source corresponding to the new SELECT value.

多路复用器有一个控制信号，命名为SELECT，当SELECT设置为“0”时，它将CKK0传播到输出，或者当SELECT设置为“1”时，将CLK1传播到输出。当SELECT变化时，可能是由于从当前时钟源的输出立即切换到下一个时钟源而引起的毛刺。当前时钟（Current Clock）是当前SELECT选择的时钟源，而下一个时钟（Next Clock）是对应于新SELECT值的时钟源。

The timing diagram in Figure 1 shows how a glitch is generated at the output, OUT CLOCK, when the SELECT control signal changes. The problem with this kind of switch is that the switch control signal can change any time with respect to the source clocks, thus creating a potential for chopping the output clock or creating a glitch at the output.

图1中的时序图显示了当SELECT控制信号发生变化时，输出时钟如何产生毛刺（glitch）。这种切换导致的问题是切换控制信号可以相对于源时钟的任何时间发生改变（本质是SELECT信号完全异步），从而产生用于切断输出时钟或在输出处产生毛刺的潜在可能。

The select control signal is most likely generated by a register driven by either of the two source clocks, which means that either it has a known timing relationship to both clocks, if both clocks are multiples of each other, or it may be asynchronous to at least one clock, if source clocks are not related in any way.

SELECT控制信号最有可能是由两个源时钟中的任一个驱动的寄存器生成的，这意味着它要么与两个时钟具有已知的时序关系，要么这两个时钟是彼此的倍数，或者如果源时钟不存在任何的关系，则它可能与至少一个时钟异步。

Switching during either clock's high state needs to be avoided without having any idea about the frequencies or phase relationship of these clocks. Fixed delay can be used to induce the gap between the start and stop time of the two source clocks, but only if a fixed relationship exists between the two clock sources. It cannot be used where either the input frequencies are not known, or the clocks are not related.

任何时钟的高电平状态下的切换都需要避免，而不需要知道这些时钟的频率或相位关系。固定延迟可以用来诱导两个源时钟的开始时间和停止时间之间的间隙，但是只有在两个时钟源之间存在固定关系时可以采用。在输入频率未知或时钟不相关的情况下，它不能被使用。

 

Figure 1 -- Clock switching multiplexer

 

Glitch protection for related clock sources

 

A solution to prevent glitch at the output of a clock switch where source clocks are multiples of each other is presented in Figure 2. A negative edge triggered D flip-flop is inserted in the selection path for each of the clock sources. Registering the selection control at negative edge of the clock, along with enabling the selection only after other clock is de-selected first, provides excellent protection against glitches at the output.

在图2中给出了防止时钟切换导致输出的毛刺的解决方案，其中时钟源是另一个·时钟的倍数关系。在每个时钟源的选择路径中插入负边沿触发的D触发器。在时钟的负边沿上用寄存器寄存一下SELECT控制信号，以及仅在其他时钟被取消选择之后才启用选择（既先屏蔽旧时钟，然后在开启新时钟），从而在输出端提供极好的防止毛刺的发生。

Registering the select signal at negative edge of the clock guarantees that no changes occur at the output while either of the clocks is at high level, thus protecting against chopping the output clock. Feedback from one clock's selection to the other enables the switch to wait for de-selection of the Current Clock before starting the propagation of the Next Clock, avoiding any glitches.

在时钟的负边缘处寄存SELECT信号保证在任意一个时钟处于高电平时时钟输出（OUT CLOCK）中没有发生变化,从而防止对输出时钟进行切割（Chopping）。从一个时钟选择到另一个时钟的反馈使得在开始下一个时钟的传播之前必须等待当前时钟的取消，从而避免任何毛刺的产生。

The figure 2 timing diagram shows how the transition of the SELECT signal from 0 to 1 first stops propagation of CLK0 to the output at the proceeding falling edge of CLK0, then starts the propagation of CLK1 to the output at following negative edge of CLK1.

图2时序图显示了SELECT信号从0到1的转换时，首先在CLK0的下降沿时停止了CLK0的输出，然后在CLK1的下降沿处的开始输出CLK1时钟到OUT CLOCK。

There are three timing paths in this circuit that need special consideration — the SELECT control signal to either one of the two negative edge triggered flip flops, the output of DFF0 to input of DFF1, and the output of DFF1 to the input of DFF0. If the signal on any of these three paths changes at the same time as the capturing edge of the destination flip flop's clock, there is a small chance that the output of that register may become meta-stable, meaning it may go to a state between an ideal "one" and an ideal "zero."

在该电路中有三个时序路径需要特别考虑：SELECT控制信号到两个负边沿触发触发器中的任一个，DFF0输出到DFF1的输入，以及DFF1的输出到DFF0的输入。如果在这三个路径中的任何一个信号与目标触发器时钟的捕获边缘（这里是下降沿）同时变化，那么该寄存器的输出可能变为亚稳态，这意味着它可能进入理想的“1”和理想的“0”之间的状态。

A meta-stable state can be interpreted differently by the clock multiplexer and the enable feedback of the other flip flop. Therefore, it is required that capturing edges of both flip flops and the launch edge of the SELECT signal should be set apart from each other to avoid any asynchronous interfacing. This can be easily accomplished by using proper multi-cycle hold constraints or minimum delay constraints, as the timing relationship is known between the two clocks.

亚稳态可以由时钟复用器和另一触发器的使能反馈来不同地解释（ps：这里不太明白）。因此，在异步接口中，需要把两个触发器的捕获边沿和SELECT信号的发射边缘（SELECT信号的上升沿）分开避免亚稳态的产生。这可以容易地通过使用适当的多周期保持约束或最小延迟约束来实现，因为两个时钟之间的时序关系是已知的。

 

Figure2 -- Glitch-free clock switching for related clocks

 

Fault tolerance

 

At chip startup time, both flip flops DFF0 and DFF1 should be reset to the "zero" state so that neither one of the clocks is propagated initially. By starting both flip flops in "zero" state, fault tolerance is built into the clock switch.

在芯片启动时间，两个触发器DFF0和DFF1都应该重置为“零”状态，使得时钟中的任何一个都不被作为初始传播。通过在“零”状态下启动触发器，将容错建立在时钟切换中。

Let's say that one of the clocks was not toggling due to a fault at startup time. If the flip flop associated with the faulty clock had started up in "one" state, it would prevent the selection of other clock as the Next Clock, and its own state is not changeable due to lack of a running clock. By starting both flip flops in "zero" state, even if one of the source clocks is not running, there is still the ability to propagate the other good clock to the output of the switch.

假设其中一个时钟由于启动时的故障而没有切换。如果与故障时钟相关联的触发器已在“一”状态启动，则将阻止选择其他时钟作为下一个时钟，并且由于缺少运行时钟，其自身状态不可改变。通过以“零”状态启动两个触发器，即使其中一个源时钟未运行，仍然能够将另一个好的时钟传播到开关的输出。

Glitch protection for unrelated clock sources

 

The previous method of avoiding a glitch at the output of a clock switch requires the two clock sources to be multiples of each other, such that user can avoid signals to be asynchronous with either one of the clock domains. There is no mechanism to handle asynchronous signals in that implementation.

上述避免时钟切换输出处的毛刺的方法需要两个时钟源彼此的倍数，使得用户可以避免信号与任一时钟域异步。 在该实现中没有处理异步信号的机制（上面的办法只是通过时序约束解决异步的问题，并没有真正解决异步的问题）。

This leads to the second method of implementing the clock switch with synchronizer circuits to avoid potential meta-stability caused by asynchronous signals. The source of asynchronous behavior could either the be SELECT signal or the feedback from one clock domain to the other, when the two clock sources are totally unrelated to each other.

这引出了实现具有同步器电路的时钟切换的第二种方法，以避免由异步信号引起的潜在的亚稳态。 当两个时钟源彼此完全无关时，异步发送的源头可以是SELECT信号或从一个时钟域到另一个时钟域的反馈。

As shown in Figure 3, protection is provided against meta-stability by adding one extra stage of positive edge triggered flip flop for each of the clock sources. The positive edge triggered flip flop in each of the selection paths, along with the existing negative edge triggered flip flop, guards against potential meta-stability, which may be caused by asynchronous SELECT signal or asynchronous feedback from one clock domain to the other.

如图3所示，通过为每个时钟源添加一个额外级的正边沿触发触发器来提供针对避免亚稳态的保护。 每个选择路径中的正边沿触发触发器以及现有的负边沿触发触发器防止潜在的亚稳态的发生，这可能是由异步SELECT信号或从一个时钟域到另一个时钟域的异步反馈引起的。

A synchronizer is simply two stages of flip flops, where the first stage helps stabilize data by latching it and later passing it on to the next stage to be interpreted by rest of the circuit.

同步器只是两级触发器，其中第一级通过锁定数据来帮助稳定数据，然后将数据传递到下一级，由电路的其余部分解释。

 

Figure 3 -- Glitch-free clock switching for unrelated clocks

 

Conclusion

 

The hazard of generating a glitch on a clock line while switching between clock sources can be avoided with very little overhead by using the design techniques presented in this article. These techniques are fully scalable and can be extended to a clock switch for more than two clocks. For multiple clock sources, the select signal for each clock source will be enabled by feedback from all the other sources.

通过使用本文中介绍的设计技术，可以通过非常小的开销避免在时钟源之间切换时在时钟线上产生毛刺的危险。 这些技术完全可扩展，可以扩展到时钟切换两个以上的时钟。 对于多个时钟源，每个时钟源的选择信号将通过所有其他源的反馈启用。

原文链接：https://www.eetimes.com/document.asp?doc_id=1202359

ALTER推荐的时钟切换电路图