GIC

Interrupt types

A device that implements this GIC architecture can manage the following types of interrupt:

Peripheral interrupt
This is an interrupt asserted by a signal to the GIC. The GIC architecture defines the This is an interrupt asserted by a signal to the GIC. The GIC architecture defines the
following types of peripheral interrupt:
- Private Peripheral Interrupt (PPI)
  This is a peripheral interrupt that is specific to a single processor.
- Shared Peripheral Interrupt (SPI)
  This is a peripheral interrupt that the Distributor can route to any of a specified
  combination of processors.
Software-generated interrupt (SGI)
This is an interrupt generated by software writing to a GICD_SGIR register in the GIC. The
system uses SGIs for interprocessor communication.
An SGI has edge-triggered properties. The software triggering of the interrupt is equivalent
to the edge transition of the interrupt request signal.
When an SGI occurs in a multiprocessor implementation, the CPUID field in the Interrupt
Acknowledge Register, GICC_IAR, or the Aliased Interrupt Acknowledge Register,
GICC_AIAR, identifies the processor that requested the interrupt.

Models for handling interrupts

In a multiprocessor implementation, there are two models for handling interrupts:

1-N model
Only one processor handles this interrupt. The system must implement a mechanism to determine
which processor handles an interrupt that is programmed to target more than one processor
N-N model
All processors receive the interrupt independently. When a processor acknowledges the interrupt,
the interrupt pending state is cleared only for that processor. The interrupt remains pending for the
other processors.

GIC logical partioning

GIC
The GIC architecture splits logically into a Distributor block and one or more CPU interface blocks. The GIC
Virtualization Extensions add one or more virtual CPU interfaces to the GIC. Therefore, as Figure 2-1 on page 2-23
shows, the logical partitioning of the GIC is as follows:

Distributor
The Distributor block performs interrupt prioritization and distribution to the CPU interface
blocks that connect to the processors in the system.
The Distributor block registers are identified by the GICD_ prefix.
CPU interfaces
Each CPU interface block performs priority masking and preemption handling for a
connected processor in the system.
CPU interface block registers are identified by the GICC_ prefix.
When describing a GIC that includes the GIC Virtualization Extensions, a CPU interface is
sometimes called a physical CPU interface, to avoid possible confusion with a virtual CPU
interface.

Implications of the 1-N model

In a multiprocessor implementation, the GIC uses the GIC 1-N model, described in Models for handling interrupts
on page 1-19, to handle peripheral interrupts that target more than one processor, that is, SPIs. This means that when
the GIC recognizes an interrupt acknowledge from one of the target processors it clears the pending state of the
interrupt on all the other targeted processors. A GIC implementation must ensure that any interrupt being handled
using the 1-N model is only acknowledged by one CPU interface, and that all other interfaces return a spurious
interrupt ID.

Interrupt prioritization

Software configures interrupt prioritization in the GIC by assigning a priority value to each interrupt source. Priority
values are 8-bit unsigned binary.
In the GIC prioritization scheme, lower numbers have higher priority, that is, the lower the assigned priority value
the higher the priority of the interrupt. Priority field value 0 always indicates the highest possible interrupt priority,
and the lowest priority value depends on the number of implemented priority levels, as Table 3-1 shows.
The GICD_IPRIORITYRn registers hold the priority value for each supported interrupt.

Preemption

A CPU interface supports signaling of higher priority pending interrupts to a target processor before an active
interrupt completes. A pending interrupt is only signaled if both:

Its priority is higher than the priority mask for that CPU interface, see Priority masking.
Its group priority is higher than that of the Running priority on the CPU interface, see Priority grouping and
Running Priority Register, GICC_RPR on page 4-142.

Preemption occurs at the time when the processor acknowledges the new interrupt, and starts to service it in
preference to the previously active interrupt or the currently running process. When this occurs, the initial active
interrupt is said to have been preempted. Starting to service an interrupt while another interrupt is still active is
sometimes described as interrupt nesting.

Priority masking

The GICC_PMR for a CPU interface defines a priority threshold for the target processor. The GIC only signals
pending interrupts with a higher priority than this threshold value to the target processor. A value of zero, the register
reset value, masks all interrupts from being signaled to the associated processor.

Priority grouping

Priority grouping uses the Binary Point Register, GICC_BPR, to split a priority value into two fields, the group
priority and the subpriority. When determining preemption, all interrupts with the same group priority are
considered to have equal priority, regardless of the subpriority. This means that there can only be one interrupt active
at each group priority.
The GIC uses the group priority field to determine whether a pending interrupt has sufficient priority to preempt an
active interrupt, as follows:
• For a pending interrupt to preempt an active interrupt, its group priority must be higher than the group priority
of the active interrupt. That is, the value of the group priority field for the new interrupt must be less than the
value of the group priority field of the Running priority.
• If there are no active interrupts on the CPU interface, the highest priority pending interrupt can be signaled
to a processor, regardless of the group priority.