Matrix Multiplier Core Design

Introduction

Matrix multiplication is a mathematical operation that is required in most signal processing and image processing applications. In this project the design and implementation of 32x32 matrix multiplier has been done. The matrix multiplication core accepts two input matrices element by element, each element is 16 bit. These elements or values are stored in 2 input buffers and after input storing is finished the core starts calculating the product matrix element by element and store each element in an output buffer.

A MATLAB simulation model is created to generate two random 32x32 Matrices and calculate the product of these two matrices, the MATLAB m code exports the generated input matrices and the result into text files. The generated text files for the two random matrices are used as an input source for a VHDL test bench to verify the operation of the designed matrix multiplication core.

MATLAB simulation model

 

The MATLAB simulation file generates two random matrices M1 and M2 each matrix is files with 32x32 random values in range between 0 to 100.

M1 = randsrc(32, 32, [0:1:100]); 

M2 = randsrc(32, 32, [0:1:100]); 

 

The MATLAB file then converts each matrix to a single vector and open two text files then fill it with the values of the vector in HEX format. These two text files will be used in the VHDL test bench to test the VHDL matrix multiplication core

fileID = fopen('input_A.txt','w');

B = reshape(M1',[],1);

fprintf(fileID,'val=\r\n');

for i=1:1:1024

    fprintf(fileID,'%s',dec2hex(B(i),4));

    fprintf(fileID,'\r\n');

end

fclose(fileID);

B = reshape(M2',[],1);

 

fileID = fopen('input_B.txt','w');

fprintf(fileID,'val=\r\n');

for i=1:1:1024

    fprintf(fileID,'%s',dec2hex(B(i),4));

    fprintf(fileID,'\r\n');

end

fclose(fileID);

 

After that the product of the two matrices is calculated. This result is also converted into hex vector and exported to an external text file to be used in comparison with the VHDL results

fclose(fileID);

Result = M1 * M2;

B = reshape(Result',[],1);

fileID = fopen('output_matlab.txt','w');

for i=1:1:1024

    fprintf(fileID,'%s',dec2hex(B(i),8));

    fprintf(fileID,'\r\n');

end

      

 

fclose(fileID);

 

VHDL Design

 

The VHDL design is consists of two parts, the control unit and the data path,

The data path consists of the following components:

• Two 16x1024 simple dual port ram:

These two memories are used as input buffers which accepts inputs from external ports and gives its output to internal multiply and accumulate circuit.

• One 64x1024 simple dual port ram:

This memory is used as output buffer which stores the results from the multiply accumulate circuit and its contents can be read from the external ports

• Two address generator counters:

These counters are used to generate the read address for the input buffers. Counter_1 counts continuously from 0 to 1023, and when it reach 1023 it restarts and counter_2 is incremented by one. By this way the address for buffer A and buffer B can be set as follow:

    ReadAddrA <= counter_2 & counter_1(4 downto 0);

    ReadAddrB <= counter_1(4 downto 0) & counter_1(9 downto 5);

 

• Multiply accumulate circuit:

The accumulator circuit accumulate the result of multiplying two elements until the complete row by column multiplications are finished and stores the result after finish. The finish of accumulation is indicated by load signal. The code of the accumulation circuit is shown below:

    process (Clock)

    begin

       if rising_edge(Clock) then

           WriteEnableC(0) <= '0';

           if(Reset='1')then

                temp <= (others=>'0');

            elsif(enable_cnt='1')then

                if(load='1' and eoc='0')then

                    WriteEnableC(0) <= '1';

                    temp <= (others=>'0');  

                    WriteDataC <=  std_logic_vector(signed(temp) + (signed(ReadDataA) * signed(ReadDataB)));

                else

                    temp <= std_logic_vector(signed(temp) + (signed(ReadDataA) * signed(ReadDataB)));

                end if;

            end if;

        end if;

    end process;

 

The control unit (finite state machine):

The control unit is responsible for detecting the start and end of storing the input values to the input buffers. And it is also responsible for enabling the accumulation circuit and the address counter. The following figure shows the state diagram of the finite state machine

During state Idle the state machine wait for the start of writing to the input buffers. In state S0 the state machine wait until the write enable is equal to zero which means that the writing to the input buffers is finished.

In state s1 the control FSM enable the address counters and enables the multiply accumulate circuit and it waits for the end of calculation signal (eoc). When eoc=1 the finite state machine go to state s2 where it generates the data ready signal and it go back to state idle.

VHDL simulation

        A test bench is written in VHDL to verify the operation of the operation of the matrix multiplication unit. The vhdl test bench use the input text files generated from the MATLAB m code to test the matrix multiplier core, and it stores the results in a text file in hex format which can then be used to compare the results with the results obtained from the MATLAB m code

 

The simulation results showed that the matrix multiplier, performed the required function correctly.