verilog语言编写4-16译码器@liuchao_L

4-16译码器verilog源文件

module my4_16(
a,
b,
c,
d,
out
);
input a;
input b;
input c;
input d;

output reg[15:0]out;

[email protected](a,b,c,d)begin
	case({a,b,c,d})
		4'b0000:out = 16'b0000_0000_0000_0001;
		4'b0001:out = 16'b0000_0000_0000_0010;
		4'b0010:out = 16'b0000_0000_0000_0100;
		4'b0011:out = 16'b0000_0000_0000_1000;
		
		4'b0100:out = 16'b0000_0000_0001_0000;
		4'b0101:out = 16'b0000_0000_0010_0000;
		4'b0110:out = 16'b0000_0000_0100_0000;
		4'b0111:out = 16'b0000_0000_1000_0000;
		
		4'b1000:out = 16'b0000_0001_0000_0000;
		4'b1001:out = 16'b0000_0010_0000_0000;
		4'b1010:out = 16'b0000_0100_0000_0000;
		4'b1011:out = 16'b0000_1000_0000_0000;
		
		4'b1100:out = 16'b0001_0000_0000_0000;
		4'b1101:out = 16'b0010_0000_0000_0000;
		4'b1110:out = 16'b0100_0000_0000_0000;
		4'b1111:out = 16'b1000_0000_0000_0000;
	endcase
end

endmodule

Test_Bench脚本测试文件

`timescale 1ns/1ns
module my4_16_tb;
reg a;
reg b;
reg c;
reg d;

wire [15:0]out;
	my4_16 my4_160(
		.a(a),
		.b(b),
		.c(c),
		.d(d),
		.out(out)
	);
	
	initial begin
		a=0;b=0;c=0;d=0;
		#200;
		a=0;b=0;c=0;d=1;
		#200;
		a=0;b=0;c=1;d=0;
		#200;
		a=0;b=0;c=1;d=1;
		#200;
		
		a=0;b=1;c=0;d=0;
		#200;
		a=0;b=1;c=0;d=1;
		#200;
		a=0;b=1;c=1;d=0;
		#200;
		a=0;b=1;c=1;d=1;
		#200;
		
		a=1;b=0;c=0;d=0;
		#200;
		a=1;b=0;c=0;d=1;
		#200;
		a=1;b=0;c=1;d=0;
		#200;
		a=1;b=0;c=1;d=1;
		#200;
		
		a=1;b=1;c=0;d=0;
		#200;
		a=1;b=1;c=0;d=1;
		#200;
		a=1;b=1;c=1;d=0;
		#200;
		a=1;b=1;c=1;d=1;
		#200;
		
		$stop;	
	end

endmodule

仿真测试结果

4-16译码器仿真结果