如何在VHDL的时钟中做2Hz的暂停？

Question

我是VHDL中的新手，我需要在VHDL程序中做一个2Hz或0.5Hz的暂停，用于计数器项目。

在另一方面，我有以下代码：

architecture behavior of Counter is 
signal q: std_logic_vector(7 downto 0); 

begin 
process(clock, choose) 
    begin 

    if clear = '1' then 
     q <= q - q; 
    else 
     if rising_edge(clock) then 
      -- when choose is '1', the process if for increment 
      if(choose = '1') then 
       case incodec is   
        when "001" => q <= q + 1; 
        when "011" => q <= q + 10; 
        when "111" => q <= q + 11; 
        when others => q <= q; 
       end case; 
      -- when choose is '0', the process if for decrement 
      elsif choose = '0' then 
       case incodec is   
        when "001" => q <= q - 1; 
        when "011" => q <= q - 10; 
        when "111" => q <= q - 11; 
        when others => q <= q; 
       end case; 
      end if; 
     end if; 
    end if; 
    case q(7 downto 4) is 
            --
     when "0000" => hex7 <= "1000000"; --0 
     when "0001" => hex7 <= "1111001"; --1 
     when "0010" => hex7 <= "0100100"; --2 
     when "0011" => hex7 <= "0110000"; --3 
     when "0100" => hex7 <= "0011001"; --4 
     when "0101" => hex7 <= "0010010"; --5 
     when "0110" => hex7 <= "0000010"; --6 
     when "0111" => hex7 <= "1111000"; --7 
     when "1000" => hex7 <= "0000000"; --8 
     when "1001" => hex7 <= "0010000"; --9 
     when "1010" => hex7 <= "0001000"; --10/A 
     when "1011" => hex7 <= "0000011"; --11/B/b 
     when "1100" => hex7 <= "1000110"; --12/C 
     when "1101" => hex7 <= "0100001"; --13/D/d 
     when "1110" => hex7 <= "0000110"; --14/E 
     when "1111" => hex7 <= "0001110"; --15/F 
     when others => hex7 <= "0111111"; -- - 
    end case; 

    case q(3 downto 0) is 
            --
     when "0000" => hex6 <= "1000000"; --0 
     when "0001" => hex6 <= "1111001"; --1 
     when "0010" => hex6 <= "0100100"; --2 
     when "0011" => hex6 <= "0110000"; --3 
     when "0100" => hex6 <= "0011001"; --4 
     when "0101" => hex6 <= "0010010"; --5 
     when "0110" => hex6 <= "0000010"; --6 
     when "0111" => hex6 <= "1111000"; --7 
     when "1000" => hex6 <= "0000000"; --8 
     when "1001" => hex6 <= "0010000"; --9 
     when "1010" => hex6 <= "0001000"; --10/A 
     when "1011" => hex6 <= "0000011"; --11/B/b 
     when "1100" => hex6 <= "1000110"; --12/C 
     when "1101" => hex6 <= "0100001"; --13/D/d 
     when "1110" => hex6 <= "0000110"; --14/E 
     when "1111" => hex6 <= "0001110"; --15/F 
     when others => hex6 <= "0111111"; -- - 
    end case; 
end behavior 

当程序编译显示以下错误：

Error (10818): Can't infer register for "q[0]" at Counter.vhd(28) because it does not hold its value outside the clock edge I don't know what is means

请帮助我:(

Answer 1

您的代码包含多个错误：

• 请勿使用Synopsys软件包进行算术运算。
  改为使用包numeric_std和signed和/或unsigned。
• q代表状态并将被合成为触发器。
  因此，在FPGA技术上，对它们进行初始化：:= (others => '0')
• clear是一个异步信号，因此将它列在灵敏度列表中。
• choose是一个同步信号，所以不要列在灵敏度列表中。
• 当您想要添加数字1,2,3时，请使用适当的整数文字或将您的文字明确指定为二进制文字。默认值是十进制。
• 使用变量将通过消除重复来缩短代码。
• 清算q应通过分配全部为零的所有零来完成：(others => '0')。
• A for循环和另一个变量可以进一步减少您的代码并删除另一大段重复的代码。
• 用户变量hex也将删除额外的寄存器阶段，这很可能不是大多数设计人员所期望的。
• 您对7段显示器的段名称进行了评论，但段通常被命名为GFEDCBA。
• 您应该将您的7段解码器放入单独的实体或函数中以提高可重用性。
• 您的7段显示代码是低活动的，但设计者应该编写高活动代码。低活性是由于电路板或显示设计而不是解码器的责任。将hex分配到hex7时可以完成反转。

下面是改进代码：

library IEEE; 
use  IEEE.std_logic_1164.all; 
use  IEEE.numeric_std.all; 


entity Counter is 
    -- ... 
end entity; 


architecture behavior of Counter is 
    signal q : unsigned(7 downto 0) := (others => '0'); 
begin 
    process(clock, clear) 
     variable decoded : positive; 
     variable hex  : std_logic_vector(13 downto 0); 
    begin 
     case incodec is   
      when "001" => decoded := 1; 
      when "011" => decoded := 2; 
      when "111" => decoded := 3; 
      when others => decoded := 0; 
     end case; 

     if clear = '1' then 
      q <= (others => '0'); 
     elsif rising_edge(clock) then 
      if(choose = '1') then  -- when choose is '1', the process if for increment 
       q <= q + decoded; 
      elsif (choose = '0') then -- when choose is '0', the process if for decrement 
       q <= q - decoded; 
      end if; 
     end if; 

     for i in 0 to 1 loop 
      case q(i*4+7 downto i*4) is   --
       when "0000" => hex(i*7+6 downto i*7) := "1000000"; --0 
       when "0001" => hex(i*7+6 downto i*7) := "1111001"; --1 
       when "0010" => hex(i*7+6 downto i*7) := "0100100"; --2 
       when "0011" => hex(i*7+6 downto i*7) := "0110000"; --3 
       when "0100" => hex(i*7+6 downto i*7) := "0011001"; --4 
       when "0101" => hex(i*7+6 downto i*7) := "0010010"; --5 
       when "0110" => hex(i*7+6 downto i*7) := "0000010"; --6 
       when "0111" => hex(i*7+6 downto i*7) := "1111000"; --7 
       when "1000" => hex(i*7+6 downto i*7) := "0000000"; --8 
       when "1001" => hex(i*7+6 downto i*7) := "0010000"; --9 
       when "1010" => hex(i*7+6 downto i*7) := "0001000"; --10/A 
       when "1011" => hex(i*7+6 downto i*7) := "0000011"; --11/b 
       when "1100" => hex(i*7+6 downto i*7) := "1000110"; --12/C 
       when "1101" => hex(i*7+6 downto i*7) := "0100001"; --13/d 
       when "1110" => hex(i*7+6 downto i*7) := "0000110"; --14/E 
       when "1111" => hex(i*7+6 downto i*7) := "0001110"; --15/F 
       when others => hex(i*7+6 downto i*7) := "0111111"; -- - 
      end case; 
     end loop; 

     hex7 <= hex(13 downto 7); 
     hex6 <= hex(6 downto 0); 
    end process; 
end architecture;