VHDL实体端口与组件端口的类型不匹配
问题描述:
我正在使用Xilinx Vivado在VHDL中使用类似MIPS的CPU。我有一个组件,用于我的BranchControl模块,它是这样的:VHDL实体端口与组件端口的类型不匹配
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity BranchControl is
Port (PL : in STD_LOGIC;
BC : in STD_LOGIC_VECTOR(3 downto 0);
PC : in STD_LOGIC_VECTOR (31 downto 0);
AD : in STD_LOGIC_VECTOR (31 downto 0);
Flags : in STD_LOGIC_VECTOR(3 downto 0);
PCLoad : out STD_LOGIC;
PCValue : out STD_LOGIC_VECTOR (31 downto 0));
end BranchControl;
architecture Behavioral of branchcontrol is
signal Z,N,P,C,V, T: std_logic;
begin
Z <= Flags(3); -- zero flag
N <= Flags(2); -- negative flag
P <= not N and not Z; -- positive flag
C <= FLags(1); -- carry flag
V <= Flags(0); -- overflow flag
T <=
'1' when (PL = '1') and (BC = "0000") and (Flags = "XXXX") else -- B
'1' when (PL = '1') and (BC = "0010") and (Flags = "1XXX") else -- BEQ
'1' when (PL = '1') and (BC = "0011") and (Flags = "0XXX") else -- BNE
'1' when (PL = '1') and (BC = "0100") and (Flags = "00XX") else -- BGT
'1' when (PL = '1') and (BC = "0101") and (Flags = "11XX") else -- BGE
'1' when (PL = '1') and (BC = "0110") and (Flags = "01XX") else -- BLT
'1' when (PL = '1') and (BC = "0111") and (Flags = "11XX") else -- BLE
'0';
with T select
PCValue <= PC+AD when '1',
PC when others;
PCLoad <= T;
end Behavioral;
我写一个仿真测试BranchControl组件,并确保其工作正常,因为我打算。这里是我的模拟:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity SimulBranchControl is
end SimulBranchControl;
architecture Behavioral of SimulBranchControl is
component BranchControl is
Port (PL : in STD_LOGIC;
BC : in STD_LOGIC_VECTOR(3 downto 0);
PC : in STD_LOGIC_VECTOR (31 downto 0);
AD : in STD_LOGIC_VECTOR (31 downto 0);
Flags : in STD_LOGIC_VECTOR(3 downto 0);
PCLoad : out STD_LOGIC;
PCValue : out STD_LOGIC_VECTOR (31 downto 0));
end component;
signal iPL : STD_LOGIC;
signal iBC : STD_LOGIC_VECTOR(3 downto 0);
signal iPC : STD_LOGIC_VECTOR(31 downto 0);
signal iAD : STD_LOGIC_VECTOR(31 downto 0);
signal iFlags : STD_LOGIC_VECTOR(3 downto 0);
signal clock : std_logic := '0';
begin
process
begin
wait for 50 ns;
clock <= not clock;
end process;
process
begin
wait until clock'event and clock='0';
iPL<='1'; iBC<="0010"; iPC<=x"00000000"; iAD<=x"00000001"; iFlags<="0000";
end process;
BC0: BranchControl port map(iPL=>PL, iBC=>BC, iPC=>PC, iAD=>AD, iFlags=>Flags);
end Behavioral;
出于某种原因,当我尝试运行Vivado仿真,我得到了阐述步一系列的错误:现在
INFO: [VRFC 10-163] Analyzing VHDL file "/home/meurer/src/acomp/L02/Project2/Project2.srcs/sim_1/new/BranchControl.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity BranchControl
INFO: [VRFC 10-163] Analyzing VHDL file "/home/meurer/src/acomp/L02/Project2/Project2.srcs/sim_1/new/SimulBranchControl.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity SimulBranchControl
ERROR: [VRFC 10-719] formal port/generic <ipl> is not declared in <branchcontrol> [/home/meurer/src/acomp/L02/Project2/Project2.srcs/sim_1/new/SimulBranchControl.vhd:43]
ERROR: [VRFC 10-704] formal pl has no actual or default value [/home/meurer/src/acomp/L02/Project2/Project2.srcs/sim_1/new/SimulBranchControl.vhd:43]
ERROR: [VRFC 10-1504] unit behavioral ignored due to previous errors [/home/meurer/src/acomp/L02/Project2/Project2.srcs/sim_1/new/SimulBranchControl.vhd:8]
INFO: [VRFC 10-240] VHDL file /home/meurer/src/acomp/L02/Project2/Project2.srcs/sim_1/new/SimulBranchControl.vhd ignored due to errors
,从我的理解这意味着我的实体BranchControl
和我在仿真中的我的组件具有不兼容的声明,但我不明白这是如此,它们看起来与我完全一样。以下是Vivado的screenshot给我的错误。
这是怎么发生的?我究竟做错了什么?
答
实例化中的组件映射是错误的方法;它应该是:
bc0: BranchControl port map (pl => ipl, bc => ibc, pc => ipc, ad => iad, flags => iflags);
通过形式关联,实体声明名称(正式端口)与实际信号名称相关联,而不是与其他对象相关联。 (例如,在BC0实例化端口映射关联列表中,“iPL => PL”应该是“PL => iPL”)。 – user1155120
你为什么要测试X位(错误)的标志?我认为你的意思是不在乎,但是,对。不关心的测试需要'?='或'std_match(...)'。 – Paebbels