FPGA内部存储器的使用-VGA驱动
这就是VGA的时序图,其中左上角为显示区域。
针对常见的两种分辨率,提供两组参数:
640*480 每秒60帧 pix_clk=25.152MHz :
localparam H_Sync = 96 ;
localparam H_BackPocrch = 48 ;
localparam H_Active = 640;
localparam H_FrontPorch = 16 ;
localparam V_Sync = 2 ;
localparam V_BackPocrch = 11 ;
localparam V_Active = 480;
localparam V_FrontPorch = 31 ;
1024*768 每秒60帧 pix_clk=65MHz :
localparam H_ACTIVE 1024
localparam H_FRONT_PORCH 24
localparam H_SYNCH 136
localparam H_BACK_PORCH 160
localparam V_ACTIVE 768
localparam V_FRONT_PORCH 3
localparam V_SYNCH 6
localparam V_BACK_PORCH 29
640*480 每秒60帧 pix_clk=25.152MHz 逻辑代码:
//分辨率使用640*480 60HZ
//clk_vga 25.152MHz
module vga_time(
input clk_vga ,
input rst_n ,
output valid ,
output reg h_vga ,
output reg v_vga
);
localparam H_Sync = 96 ;
localparam H_BackPocrch = 48 ;
localparam H_Active = 640;
localparam H_FrontPorch = 16 ;
localparam H_Total = H_Sync+H_BackPocrch+H_Active+H_FrontPorch;//
localparam V_Sync = 2 ;
localparam V_BackPocrch = 11 ;
localparam V_Active = 480;
localparam V_FrontPorch = 31 ;
localparam V_Total = V_Sync+V_BackPocrch+V_Active+V_FrontPorch ;
reg [10:0] h_cnt ,
reg [10:0] v_cnt ,
[email protected](posedge clk_vga )begin
if(rst_n)
begin
h_cnt <= 'd0 ;
v_cnt <= 'd0 ;
end
else
begin
h_cnt <= h_cnt == ( H_Total -1'b1 ) ? 'd0 : h_cnt + 1'b1 ;
if(h_cnt==H_Total-1)
v_cnt <= (v_cnt == V_Total-1'b1) ? 'd0 :v_cnt + 1'b1;
else
v_cnt <= v_cnt;
end
end
[email protected](posedge clk_vga )begin
if( rst_n )
h_vga <= 1'b0;
else if(h_cnt==H_Active + H_FrontPorch-1)
h_vga <= 1'b0;
else if(h_cnt==H_Active + H_FrontPorch+H_Sync-1)
h_vga <= 1'b1;
end
[email protected](posedge clk_vga )begin
if( rst_n )
v_vga <= 1'b0;
else if(h_cnt == H_Total-1)begin
if(v_cnt==V_Active + V_FrontPorch-1)
v_vga <= 1'b0;
else if(v_cnt==V_Active + V_FrontPorch+V_Sync-1)
v_vga <= 1'b1;
end
end
reg h_en ;
[email protected](posedge clk_vga)begin
if(rst_n)
h_en <= 1'b0;
else if(h_cnt==H_Total-1 )
h_en <= 1'b1;
else if(h_cnt==H_Active-1)
h_en <= 1'b0;
end
reg v_en ;
[email protected](posedge clk_vga )begin
if(rst_n)
v_en <= 1'b0;
else if(h_cnt==H_Total-1 )begin
if(v_cnt == V_Total-1)
v_en <= 1'b1;
else if(v_cnt==H_Active-1)
v_en <= 1'b0;
end
end
assign valid = v_en & h_en ;
endmodule