S32K系列S32K144学习笔记——比较器CMP

S32K系列S32K144学习笔记——比较器CMP
本例程基以下如图所示接口操作，MCU为S32K144，开发平台S32DSworkspace
功能描述：设置PTE8为比较输入，通过芯片内置比较器，把比较结果通过PTE3输出
如有错误，麻烦帮忙指出，谢谢！

#include "S32K144.h" /* include peripheral declarations S32K144 */
#include "s32_core_cm4.h"

void WDOG_disable (void)
{
	WDOG->CNT=0xD928C520; 	 //解锁看门狗
	WDOG->TOVAL=0x0000FFFF;	 //把时间配置为最大
	WDOG->CS = 0x00002100;   //关闭看门狗
}
void SOSC_init_8MHz(void)
{
	SCG->SOSCDIV=0x00000101;  // SOSCDIV1 & SOSCDIV2 =1: divide by 1
	SCG->SOSCCFG=0x00000024;  /* Range=2: Medium freq (SOSC betw 1MHz-8MHz)*/
                        	  /* HGO=0:   Config xtal osc for low power */
                              /* EREFS=1: Input is external XTAL */
	while(SCG->SOSCCSR & SCG_SOSCCSR_LK_MASK); /* Ensure SOSCCSR unlocked */
	SCG->SOSCCSR=0x00000001;  /* LK=0:          SOSCCSR can be written */
                        	  /* SOSCCMRE=0:    OSC CLK monitor IRQ if enabled */
                        	  /* SOSCCM=0:      OSC CLK monitor disabled */
                        	  /* SOSCERCLKEN=0: Sys OSC 3V ERCLK output clk disabled */
                        	  /* SOSCLPEN=0:    Sys OSC disabled in VLP modes */
                        	  /* SOSCSTEN=0:    Sys OSC disabled in Stop modes */
                        	  /* SOSCEN=1:      Enable oscillator */
	while(!(SCG->SOSCCSR & SCG_SOSCCSR_SOSCVLD_MASK)); /* Wait for sys OSC clk valid */
}

void SPLL_init_160MHz(void)
{
	while(SCG->SPLLCSR & SCG_SPLLCSR_LK_MASK); /* Ensure SPLLCSR unlocked */
	SCG->SPLLCSR = 0x00000000;  /* SPLLEN=0: SPLL is disabled (default) */
	SCG->SPLLDIV = 0x00000302;  /* SPLLDIV1 divide by 2; SPLLDIV2 divide by 4 */
	SCG->SPLLCFG = 0x00180000;  /* PREDIV=0: Divide SOSC_CLK by 0+1=1 */
                          		/* MULT=24:  Multiply sys pll by 4+24=40 */
                          		/* SPLL_CLK = 8MHz / 1 * 40 / 2 = 160 MHz */
	while(SCG->SPLLCSR & SCG_SPLLCSR_LK_MASK); /* Ensure SPLLCSR unlocked */
	SCG->SPLLCSR = 0x00000001; /* LK=0:        SPLLCSR can be written */
                         	   /* SPLLCMRE=0:  SPLL CLK monitor IRQ if enabled */
                         	   /* SPLLCM=0:    SPLL CLK monitor disabled */
                         	   /* SPLLSTEN=0:  SPLL disabled in Stop modes */
                         	   /* SPLLEN=1:    Enable SPLL */
 	while(!(SCG->SPLLCSR & SCG_SPLLCSR_SPLLVLD_MASK)); /* Wait for SPLL valid */
}

void NormalRUNmode_40MHz (void)
{
	/* Change to normal RUN mode with 8MHz SOSC, 80 MHz PLL*/
	SCG->RCCR=SCG_RCCR_SCS(6)     /* PLL as clock source*/
	|SCG_RCCR_DIVCORE(0b11)       /* DIVCORE=3, div. by 4: Core clock = 160/4 MHz = 40 MHz*/
	|SCG_RCCR_DIVBUS(0b11)        /* DIVBUS=3, div. by 4: bus clock = 160/4 MHz = 40 MHz*/
	|SCG_RCCR_DIVSLOW(0b111);     /* DIVSLOW=7, div. by 8: SCG slow, flash clock= 160/8 MHz = 20MHZ*/
	while (((SCG->CSR & SCG_CSR_SCS_MASK) >> SCG_CSR_SCS_SHIFT ) != 6) {}
    /* Wait for sys clk src = SPLL */
}
void CMP0_Init(void)
{
	PCC->PCCn[PCC_PORTE_INDEX] |= PCC_PCCn_CGC_MASK; //使能PTE端口时钟
	PORTE->PCR[8] = PORT_PCR_MUX(0); //Port E8: MUX = ALT0,CMP0_INT3 PTE8端口复用为CMP0_INT3
	PORTE->PCR[3] = PORT_PCR_MUX(7); //Port E3: MUX = ALT7,CMP0_OUT PTE3端口复用为CMP0_OUT
	PCC->PCCn[PCC_CMP0_INDEX] |= PCC_PCCn_CGC_MASK; //使能CMP0时钟

	CMP0->C0 = 0x00001640;//高速转换，不反转，经过过滤输出，4采样数

	CMP0->C1 = 0x08089F7A;//VDDA为参考电压，比较器正端口INPSEL为自模拟8-1 mux
	//比较器负端口为8位DAC输出，打开通道3输入，DAC使能
	//PSEL选择IN3 ，MSEL选择IN7（没有用）
	//DAC电压选择DACO = (Vin/256) × (VOSEL[7:0] + 1) = 2.4V


	CMP0->C2 = 0xA6000200;//循环使能，负端口固定，IN3为固定输入， INITMOD = 10 > ((30us / 8us) = 3.75)

	CMP0->C2 |= (0xFF << 16); // Clear register flags CHxF  

	CMP0->C0 |= (1 << 8);     // Enable comparator
}

int main(void)
{
	WDOG_disable();                   //关闭看门狗

	SOSC_init_8MHz();                 //配置系统振荡器为外部8MHZ
	SPLL_init_160MHz();               //使用SOSC 8MHZ配置SPLL 为160 MHz
	NormalRUNmode_40MHz();            //配置系列时钟40MHz, 40MHz总线时钟
	
	CMP0_Init();                       //配置比较器 PTE8输入 PTE3输出

	while(1)
	{

	}
	return 0;
}

CMP以CMP_C0,CMP_C1,CMP_C2进行相关的配置，不熟悉的可以根据下图来看，一环环的看电路怎么输出怎么输入，从而进行相关的配置